Patents by Inventor Robert A. Walters

Robert A. Walters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10822231
    Abstract: Novel and useful quantum structures that provide various control functions. Particles are brought into close proximity to interact with one another and exchange information. After entanglement, the particles are moved away from each other but they still carry the information contained initially. Measurement and detection are performed on the particles from the entangled ensemble to determine whether the particle is present or not in a given qdot. A quantum interaction gate is a circuit or structure operating on a relatively small number of qubits. Quantum interaction gates implement several quantum functions including a controlled NOT gate, quantum annealing gate, controlled SWAP gate, a controlled Pauli rotation gate, and ancillary gate. These quantum interaction gates can have numerous shapes including double V shape, H shape, X shape, L shape, I shape, etc.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 3, 2020
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 10804246
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 13, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10800654
    Abstract: Novel and useful quantum structures that provide various control functions. Particles are brought into close proximity to interact with one another and exchange information. After entanglement, the particles are moved away from each other but they still carry the information contained initially. Measurement and detection are performed on the particles from the entangled ensemble to determine whether the particle is present or not in a given qdot. A quantum interaction gate is a circuit or structure operating on a relatively small number of qubits. Quantum interaction gates implement several quantum functions including a controlled NOT gate, quantum annealing gate, controlled SWAP gate, a controlled Pauli rotation gate, and ancillary gate. These quantum interaction gates can have numerous shapes including double V shape, H shape, X shape, L shape, I shape, etc.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: October 13, 2020
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Publication number: 20200318520
    Abstract: The invention relates to a method for operating an internal combustion engine installed in a vehicle, in particular a diesel engine, in which the instantaneous concentration of a pollutant contained in the exhaust gas, in particular the NOx concentration in the exhaust gas, is measured or calculated in the flow direction after an exhaust gas aftertreatment. Using the determined pollutant concentration, the predefined distance- and/or power-based compliance with pollutant limiting values in mg/km or mg/kWh are monitored by means of specifically influencing the operating parameters of the internal combustion engine and/or an exhaust gas after treatment system in regulated form.
    Type: Application
    Filed: May 19, 2017
    Publication date: October 8, 2020
    Applicant: TECHNISCHE UNIVERSITÄT DRESDEN
    Inventors: Robert WALTER, Tilo ROSS, Hans ZELLBECK
  • Patent number: 10793431
    Abstract: Novel and useful quantum structures that provide various control functions. Particles are brought into close proximity to interact with one another and exchange information. After entanglement, the particles are moved away from each other but they still carry the information contained initially. Measurement and detection are performed on the particles from the entangled ensemble to determine whether the particle is present or not in a given qdot. A quantum interaction gate is a circuit or structure operating on a relatively small number of qubits. Quantum interaction gates implement several quantum functions including a controlled NOT gate, quantum annealing gate, controlled SWAP gate, a controlled Pauli rotation gate, and ancillary gate. These quantum interaction gates can have numerous shapes including double V shape, H shape, X shape, L shape, I shape, etc.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: October 6, 2020
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 10796835
    Abstract: Embodiments of electronic devices, such as integrated circuit (IC) packages are disclosed. In one embodiment, an electronic device includes a first substrate and a second substrate. The first substrate has a first substrate body and a first inductor portion integrated into the first substrate body. Additionally, the second substrate comprises a second substrate body and a second inductor portion integrated into the second substrate body. The second substrate is mounted on the first substrate such that such that the second inductor portion is positioned over the first inductor portion and such that the second inductor portion is electrically connected to the first inductor portion so that the first inductor portion and the second inductor portion form a three dimensional (3D) inductor. By using two substrates, the 3D inductor can be increased in height while still allowing the substrates to be miniaturized and standardized for an IC package.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 6, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Michael F. Zybura, George Maxim, Dirk Robert Walter Leipold, John August Orlowski, Baker Scott
  • Patent number: 10784149
    Abstract: The present disclosure relates to an air-cavity module having a thinned semiconductor die and a mold compound. The thinned semiconductor die includes a back-end-of-line (BEOL) layer, an epitaxial layer over the BEOL layer, and a buried oxide (BOX) layer with discrete holes over the epitaxial layer. The epitaxial layer includes an air-cavity, a first device section, and a second device section. Herein, the air-cavity is in between the first device section and the second device section and directly in connection with each discrete hole in the BOX layer. The mold compound resides directly over at least a portion of the BOX layer, within which the discrete holes are located. The mold compound does not enter into the air-cavity through the discrete holes.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 22, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10773990
    Abstract: An optical fiber production system is provided which includes a slow-cooling device and a purge device positioned above the slow-cooling device. The purge device includes a tube defining an inlet. An optical fiber extends through the slow-cooling device and the purge device. The purge device is configured to inject a purge gas through the inlet and against the optical fiber.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: September 15, 2020
    Assignee: Corning Incorporated
    Inventors: John Michael Jewell, Nikolaos Pantelis Kladias, Robert Walter Nason, Bruce Warren Reding, Edward Barry Richter, Daniel Paul Veber, Chunfeng Zhou
  • Publication number: 20200274031
    Abstract: A method for producing an optoelectronic component by providing a semiconductor layer sequence on a substrate where the semiconductor layer sequence is configured to emit radiation. The method may further include applying a contact layer to the semiconductor layer sequence where the contact layer has a layer thickness of at most 10 nm. The method may further include applying a reflective layer to the contact layer and applying a barrier layer directly to the reflective layer.
    Type: Application
    Filed: September 26, 2018
    Publication date: August 27, 2020
    Inventors: Christoph Schwarzmaier, Martin Mandl, Robert Walter, Roland Stieglmeier, Michael Schmal
  • Patent number: 10756675
    Abstract: A broadband power amplifier circuit is provided. The broadband power amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal to an output power based on a bias voltage and a supply voltage. Given that the output power of the RF signal may rise and fall from time to time, the broadband power amplifier circuit is configured to opportunistically increase or decrease the bias voltage in a defined future time (e.g., a future time slot or a future symbol duration) based on the output power in the defined future time. When necessary, the broadband power amplifier may be further configured to adjust the supply voltage and/or attenuate the RF signal based on the output power. As such, it may be possible to maintain class-A operation mode for the amplifier circuit. As a result, the amplifier circuit may maintain linearity and avoid memory effect with improved efficiency.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 25, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, Baker Scott, Toshiaki Moriuchi, George Maxim
  • Publication number: 20200255319
    Abstract: Vaporizers and systems for vaporizing liquid precursor for forming glass optical fiber preforms are provided. The vaporizer includes an expansion chamber at least partially enclosed by a side wall, the expansion chamber comprising an upper end and a lower end with the side wall disposed between the upper end and the lower end. The vaporizer further includes a closed-loop liquid delivery conduit positioned in the expansion chamber proximate to the upper end of the expansion chamber, wherein the closed-loop liquid delivery conduit comprises a plurality of nozzles oriented to direct a spray of liquid precursor onto an inner surface of the side wall. Further, the vaporizer includes at least one supply conduit positioned proximate the upper end of the expansion chamber and coupled to the closed-loop liquid delivery conduit, and a vapor delivery outlet coupled to the expansion chamber and configured to direct vaporized liquid precursor from the expansion chamber.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 13, 2020
    Inventors: Stephen Mitchell Carlton, Paul Andrew Chludzinski, Jonathan Robert Greveling, Nikolaos Pantelis Kladias, Robert Walter Nason, Abhijit Rao
  • Patent number: 10742253
    Abstract: A radio frequency (RF) front-end apparatus is provided. In examples discussed herein, the RF front-end apparatus can be configured to communicate RF signals in millimeter wave (mmWave) RF frequencies (e.g., ?12 GHz). The RF front-end apparatus includes an RF front-end circuit and an antenna element. The RF front-end circuit includes a transmit path and a receive path for transmitting and receiving RF signals, respectively. The antenna element includes an input port(s) and an output port(s) that are coupled to the transmit path and the receive path, respectively. The antenna element can be configured to enable impedance matching between the input port(s) and the transmit path, as well as between the output port(s) and the receive path. As a result, it may be possible to reduce insertion losses in the RF front-end circuit, thus helping to improve performance of the RF front-end apparatus, particularly in support of mmWave communications.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 11, 2020
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Dirk Robert Walter Leipold, Wolfram C. Stiebler
  • Publication number: 20200247342
    Abstract: A vehicle door includes a trim panel coupled to a frame. A single-piece armrest substrate is coupled with the frame. The armrest substrate is a three-dimensionally printed member having interior walls that are printed within the armrest substrate according to a virtual force model generated during a virtual impact scenario. The interior walls define a plurality of voids defined within the armrest substrate.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 6, 2020
    Applicant: Ford Global Technologies, LLC
    Inventors: Michael James Whitens, Robert D. Bedard, Siddharthan Selvasekar, Amit Chakravarty, Robert Walter Bartus
  • Publication number: 20200227523
    Abstract: Novel and useful semiconductor structures using preferential tunneling through thin insulator layers. Semiconductor quantum structures are implemented using tunneling through a thin oxide layer. The quantum dots are fabricated with semiconductor wells, 3D fins or combinations thereof, while the tunneling path and any optional quantum transport path is implemented with gate layers. The oxide layer between the gate and the well is thin enough in the nanometer semiconductor processes to permit significant tunneling. Having a thin oxide layer on only one side of the well, while having thick oxide layers on all other sides, results in a preferential tunneling direction where tunneling is restricted to a small area resulting in aperture tunneling. The advantage being constraining quantum transport to a very narrow path, which can be approximated as unidimensional. In alternative embodiments, more than one preferential tunneling direction may be used. These techniques can be used in both planar and 3D (e.g.
    Type: Application
    Filed: January 20, 2020
    Publication date: July 16, 2020
    Applicant: equal1.labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Publication number: 20200227522
    Abstract: A novel and useful modified semiconductor process having staircase active well shapes that provide variable distances between pairs of locations (i.e. quantum dots) resulting in modulation of the quantum interaction strength from weak/negligible at large separations to moderate and then strong at short separations. To achieve a modulation of the distance between pairs of locations, diagonal, lateral, and vertical quantum particle/state transport is employed. As examples, both implementations of semiconductor quantum structures with tunneling through an oxide layer and with tunneling through a local well depleted region are disclosed. These techniques are applicable to both planar semiconductor processes and 3D (e.g. Fin-FET) semiconductor processes. Optical proximity correction is used to accommodate the staircase well layers. Each gate control circuit in the imposer circuitry functions to control more than one set of control gates.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 16, 2020
    Applicant: equal1.labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 10715133
    Abstract: A radio frequency switch having an N number of switch cells coupled in series is disclosed. Each of the switch cells includes a field-effect transistor (FET), wherein a source of switch cell 1 is coupled to a first port, a drain of switch cell N is coupled to a second port, and a drain of switch cell X is coupled to a source of switch cell X+1 for switch cell 1 through switch cell N. A first diode stack has a first anode coupled to the body of switch cell X and a first cathode coupled to a drain of switch cell X+1 for switch cell 1 through switch cell N?1, and a second diode stack has a second anode coupled to the body of switch cell X and a second cathode coupled to the source of switch cell X?1 for switch cell 2 through switch cell N.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: July 14, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Hideya Oshima, Dirk Robert Walter Leipold
  • Publication number: 20200220065
    Abstract: A novel and useful modified semiconductor fabrication technique for realizing reliable semiconductor quantum structures. Quantum structures require a minimization of the parasitic capacitance of the control gate and the quantum well. The modified semiconductor process eliminates the fabrication of the metal, contact, and optionally the raised diffusion layers from the quantum wells, thereby resulting in much lower well and gate capacitances and therefore larger Coulomb blockade voltages. This allows easier implementation of the electronic control circuits in that they can have larger intrinsic noise and relaxed analog resolution. Several processes are disclosed including implementations of semiconductor quantum structures with tunneling through an oxide layer as well as tunneling through a local well depleted region. These techniques can be used in both planar semiconductor processes and 3D, e.g., FinFET, semiconductor processes. A dedicated process masking step is used for realizing the raised diffusions.
    Type: Application
    Filed: January 5, 2020
    Publication date: July 9, 2020
    Applicant: equal1.labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 10707095
    Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: July 7, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Publication number: 20200198031
    Abstract: Herein a chainsaw (1) is disclosed comprising a guide bar (3) and a chain (5) moveably arranged around the guide bar (3). The chainsaw (1) comprises an motor (9) comprising a motor shaft (11), wherein the motor (9) is configured to drive the chain (5) via the motor shaft (11). The chainsaw (1) further comprises a tension estimation arrangement (13) configured to sense a load on the motor shaft (11), and configured to estimate the tension of the chain (5) around the guide bar (3) on the basis of the sensed load on the motor shaft (11). The present disclosure further relates to a method of estimating tension of a chain (5) of a chainsaw (1).
    Type: Application
    Filed: June 7, 2018
    Publication date: June 25, 2020
    Inventors: Robert Walter Schriever, E. Arnold Fie, Garrett Sherman, Victor Stramenga
  • Patent number: D901656
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: November 10, 2020
    Inventors: Walter Wardrop, Nicholas Barber, Robert Walter