Abstract: Examples of methods and systems for compensating for the timing delay caused by the winding impedance of the motor coils and/or for non-ideal rotor magnet shapes and positions are disclosed. The example methods and systems may include generating a synthesized commutation signal compensating for non-ideal magnet shapes and positions (e.g., asymmetrical magnet positions) on a rotor and/or compensates for the timing delay caused by the winding impedance of the motor coils.

Abstract: Examples of methods and systems for compensating for the timing delay caused by the winding impedance of the motor coils and/or for non-ideal rotor magnet shapes and positions are disclosed. The example methods and systems may include generating a synthesized commutation signal compensating for non-ideal magnet shapes and positions (e.g., asymmetrical magnet positions) on a rotor and/or compensates for the timing delay caused by the winding impedance of the motor coils.

Abstract: A method of operating a brushless direct current motor is provided that generates a rotor position dependent pulse width modulation waveform. The waveform can improve motor efficiency and reduce torque variation.

Abstract: A method of operating a brushless direct current motor is provided that generates a rotor position dependent pulse width modulation waveform. The waveform can improve motor efficiency and reduce torque variation.

Abstract: A method of operating a brushless direct current motor is provided that generates a rotor position dependent pulse width modulation waveform. The waveform can improve motor efficiency and reduce torque variation.

Abstract: A method of operating a brushless direct current motor is provided that generates a rotor position dependent pulse width modulation waveform. The waveform can improve motor efficiency and reduce torque variation.

Abstract: A digital time delay circuit is provided in which fabrication process variations and temperature effects on the switching threshold level of digital circuits utilized in the timing delay circuits are substantially eliminated.

Abstract: A method of operating a direct current motor fan assembly is provided in which a motor controller operates to apply full power to kick-start a motor to overcome static forces. As soon as a sensor determines that the motor has begun to rotate, the motor controller changes the motor drive level from full power to a predetermined lower level to maintain a desired rotational speed.

Abstract: A motor controller for a direct current motor includes a first node receiving first PWM signals having a duty cycle indicative of a desired rotational speed of said motor and an input node receiving second digital signals, the frequency of said second signals indicative of the rotational speed of said motor. A frequency-to-PWM circuit is coupled to the input node to provide second PWM signals having a duty cycle corresponding to the rotational speed of the motor. A duty cycle comparator has a first input coupled to the first node and a second input coupled to the second node to generate a control signal for controlling the rotational speed of the motor.

Abstract: A method and apparatus is provided for processing signals from a Hall-effect device arrangement coupled to a monolithic brushless DC motor where the motor is driven by a PWM circuit providing PWM drive signals.

Abstract: A duty cycle comparator is described for comparing the duty cycles of two digital signals. The duty cycle comparator comprises a first controllable current source, a second controllable current source and a charge accumulation device. The comparator provides an output signal that is representative of the difference between the duty cycles independent of the frequency of the two digital signals.

Abstract: A method and apparatus is provided for processing signals from a Hall-effect device arrangement coupled to a monolithic brushless DC motor where the motor is driven by a PWM circuit providing PWM drive signals.

Abstract: In accordance with the principles of the invention, an integrated circuit comprises a substrate having a first FET formed on the substrate. The first FET has a first terminal coupleable to a load, a second terminal and a control terminal. The second terminal is connected to the substrate. The substrate comprises a parasitic body diode coupled between the first terminal and the substrate. The body diode is disposed such that it becomes conductive when a reverse voltage across the FET first terminal and the substrate is at least a first diode forward voltage. A voltage detector is formed on the substrate. The voltage detector has a first input coupled to the FET first terminal, a second input coupled to the substrate, and an output coupled to the FET control terminal. The voltage detector is responsive to a reverse voltage level at the FET first terminal that is less than the first diode forward voltage to turn the FET on for the duration of a reverse voltage having at least said reverse voltage level.

Abstract: A method and apparatus is provided for processing signals from a Hall effect device arrangement coupled to a monolithic brushless DC motor where the motor is driven by a PWM circuit providing PWM drive signals.

Abstract: A method and apparatus is provided for processing signals from a Hall effect device arrangement coupled to a monolithic brushless DC motor where the motor is driven by a PWM circuit providing PWM drive signals.

Abstract: A method of operating a direct current motor fan assembly is provided in which a motor controller operates to apply full power to kick-start a motor to overcome static forces. As soon as a sensor determines that the motor has begun to rotate, the motor controller changes the motor drive level from full power to a predetermined lower level to maintain a desired rotational speed.

Abstract: A control circuit for a direct current motor is described. In accordance with the principles of the invention, a duty cycle comparator is provided to control the speed of the motor.

Abstract: A duty cycle comparator is described for comparing the duty cycles of two digital signals. The duty cycle comparator comprises a first controllable current source, a second controllable current source and a charge accumulation device. The comparator provides an output signal that is representative of the difference between the duty cycles independent of the frequency of the two digital signals.

Abstract: A digital time delay circuit is provided in which fabrication process variations and temperature effects on the switching threshold level of digital circuits utilized in the timing delay circuits are substantially eliminated.

Abstract: In accordance with the principles of the invention, an integrated circuit comprises a substrate having a first FET formed on the substrate. The first FET has a first terminal coupleable to a load, a second terminal and a control terminal. The second terminal is connected to the substrate. The substrate comprises a parasitic body diode coupled between the first terminal and the substrate. The body diode is disposed such that it becomes conductive when a reverse voltage across the FET first terminal and the substrate is at least a first diode forward voltage. A voltage detector is formed on the substrate. The voltage detector has a first input coupled to the FET first terminal, a second input coupled to the substrate, and an output coupled to the FET control terminal. The voltage detector is responsive to a reverse voltage level at the FET first terminal that is less than the first diode forward voltage to turn the FET on for the duration of a reverse voltage having at least said reverse voltage level.