Abstract: Described embodiments provide an interleaved sampler having N sample and hold circuits for sampling an input signal, and M multiplexers. Each multiplexer is adapted to couple all N of the plurality of sample and hold circuits to a respective output of the interleaved sampler. The interleaved sampler samples at a sample rate of fs, has an interleaved sampling period of M/fs, where M is greater than one and less than N. Because there are more sample and hold circuits than there are samples taken during an interleaved sampling period, different combinations of the sample and hold circuits are used from interleaved sample period to interleaved sample period. This reduces spurious tones generated from offset voltages when using interleaved sample and hold circuits. The order of the sample and hold circuits are clocked might be random, pseudorandom, or a fixed pattern longer than the interleaved sampling period.

Abstract: Described embodiments provide an interleaved sampler having N sample and hold circuits for sampling an input signal, and M multiplexers. Each multiplexer is adapted to couple all N of the plurality of sample and hold circuits to a respective output of the interleaved sampler. The interleaved sampler samples at a sample rate of fs, has an interleaved sampling period of M/fs, where M is greater than one and less than N. Because there are more sample and hold circuits than there are samples taken during an interleaved sampling period, different combinations of the sample and hold circuits are used from interleaved sample period to interleaved sample period. This reduces spurious tones generated from offset voltages when using interleaved sample and hold circuits. The order of the sample and hold circuits are clocked might be random, pseudorandom, or a fixed pattern longer than the interleaved sampling period.