Patents by Inventor Robert Alan Neidorff
Robert Alan Neidorff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11264369Abstract: In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.Type: GrantFiled: April 27, 2020Date of Patent: March 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Barry Jon Male, Benjamin Stassen Cook, Robert Alan Neidorff, Steve Kummerl
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Publication number: 20200258874Abstract: In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Inventors: Barry Jon Male, Benjamin Stassen Cook, Robert Alan Neidorff, Steve Kummerl
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Patent number: 10727730Abstract: Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.Type: GrantFiled: August 1, 2019Date of Patent: July 28, 2020Assignee: Texas Instruments IncorporatedInventors: Robert Alan Neidorff, Joseph Maurice Khayat
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Patent number: 10636778Abstract: In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.Type: GrantFiled: September 10, 2018Date of Patent: April 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Barry Jon Male, Benjamin Stassen Cook, Robert Alan Neidorff, Steve Kummerl
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Patent number: 10529796Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.Type: GrantFiled: November 1, 2018Date of Patent: January 7, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Barry Jon Male, Robert Alan Neidorff
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Publication number: 20190356212Abstract: Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.Type: ApplicationFiled: August 1, 2019Publication date: November 21, 2019Inventors: Robert Alan Neidorff, Joseph Maurice Khayat
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Patent number: 10424551Abstract: In described examples of forming an integrated circuit wave device, a method includes: (a) affixing an integrated circuit die relative to a substrate; (b) creating a form relative to the integrated circuit die and the substrate; and (c) forming a wave shaping member having a shape conforming at least in part to a shape of the form.Type: GrantFiled: March 6, 2018Date of Patent: September 24, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Barry Jon Male, Benjamin Cook, Robert Alan Neidorff, Steve Kummerl
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Patent number: 10425000Abstract: Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.Type: GrantFiled: August 21, 2017Date of Patent: September 24, 2019Assignee: Texas Instruments IncorporatedInventors: Robert Alan Neidorff, Joseph Maurice Khayat
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Publication number: 20190144267Abstract: Described examples include sensor apparatus and integrated circuits having a package structure with an internal cavity and an opening that connects of the cavity with an ambient condition of an exterior of the package structure, and an electronic sensor structure mechanically supported by wires in the cavity and including a sensing surface exposed to the cavity to sense the ambient condition of an exterior of the package structure.Type: ApplicationFiled: January 14, 2019Publication date: May 16, 2019Inventors: Barry Jon Male, Benjamin Cook, Robert Alan Neidorff, Steve Kummerl
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Publication number: 20190081133Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.Type: ApplicationFiled: November 1, 2018Publication date: March 14, 2019Inventors: Benjamin Stassen Cook, Barry Jon Male, Robert Alan Neidorff
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Publication number: 20190058394Abstract: Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.Type: ApplicationFiled: August 21, 2017Publication date: February 21, 2019Inventors: Robert Alan Neidorff, Joseph Maurice Khayat
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Patent number: 10179730Abstract: Disclosed examples include sensor apparatus and integrated circuits having a package structure with an internal cavity and an opening that connects of the cavity with an ambient condition of an exterior of the package structure, and an electronic sensor structure mechanically supported by wires in the cavity and including a sensing surface exposed to the cavity to sense the ambient condition of an exterior of the package structure.Type: GrantFiled: December 8, 2016Date of Patent: January 15, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Barry Jon Male, Benjamin Cook, Robert Alan Neidorff, Steve Kummerl
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Publication number: 20190006338Abstract: In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.Type: ApplicationFiled: September 10, 2018Publication date: January 3, 2019Inventors: Barry Jon Male, Benjamin Stassen Cook, Robert Alan Neidorff, Steve Kummerl
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Patent number: 10121847Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.Type: GrantFiled: March 17, 2017Date of Patent: November 6, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Barry Jon Male, Robert Alan Neidorff
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Patent number: 10110220Abstract: In some embodiments, a system comprises a power metal oxide semiconductor field effect transistor (MOSFET) configured to provide power in the system, a plurality of auxiliary MOSFETs, and a switch network configured to switchably and simultaneously couple a first of the plurality of auxiliary MOSFETs to the power MOSFET and a second of the plurality of auxiliary MOSFETs to a feedback voltage regulator. The switch network is further configured to switchably and simultaneously couple the first of the plurality of auxiliary MOSFETs to the feedback voltage regulator and the second of the plurality of auxiliary MOSFETs to the power MOSFET. The feedback voltage regulator is configured to cause a voltage at one or more of the plurality of auxiliary MOSFETs to match a voltage at the power MOSFET.Type: GrantFiled: June 8, 2017Date of Patent: October 23, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Robert Alan Neidorff
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Publication number: 20180269272Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.Type: ApplicationFiled: March 17, 2017Publication date: September 20, 2018Inventors: Benjamin Stassen Cook, Barry Jon Male, Robert Alan Neidorff
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Patent number: 10074639Abstract: Disclosed examples include integrated circuits with a leadframe structure, a first circuit structure including a light source configured to generate a light signal along an optical path, a second circuit structure including a light sensor facing the optical path to receive the light signal, and a molded package structure enclosing portions of the leadframe structure, the molded package structure having a cavity defined by an interior surface of the molded package structure, the optical path extending in the cavity between the first and second circuit structures.Type: GrantFiled: December 30, 2016Date of Patent: September 11, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Barry Jon Male, Benjamin Cook, Robert Alan Neidorff, Steve Kummerl
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Publication number: 20180197830Abstract: In described examples of forming an integrated circuit wave device, a method includes: (a) affixing an integrated circuit die relative to a substrate; (b) creating a form relative to the integrated circuit die and the substrate; and (c) forming a wave shaping member having a shape conforming at least in part to a shape of the form.Type: ApplicationFiled: March 6, 2018Publication date: July 12, 2018Inventors: Barry Jon Male, IV, Benjamin Cook, Robert Alan Neidorff, Steve Kummerl
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Publication number: 20180190556Abstract: In a described example, an apparatus includes: an integrated circuit die having multiple terminals; a leadframe having leads for external connections, at least some of the leads electrically coupled to at least one of the multiple terminals of the integrated circuit die; a first electrode having a first end portion; a second electrode having a second end portion positioned proximal to and spaced apart from the first end portion of the first electrode, the first end portion and the second end portion spaced by a spark gap; encapsulation material surrounding the integrated circuit die to form a packaged integrated circuit having a cavity surrounding the first end portion, the second end portion, and the spark gap so that the first end portion of the first electrode, the second end portion of the second electrode and the spark gap are spaced from the encapsulation material.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Barry Jon Male, Steve Kummerl, Robert Alan Neidorff, Benjamin Stassen Cook
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Publication number: 20180190628Abstract: Disclosed examples include integrated circuits with a leadframe structure, a first circuit structure including a light source configured to generate a light signal along an optical path, a second circuit structure including a light sensor facing the optical path to receive the light signal, and a molded package structure enclosing portions of the leadframe structure, the molded package structure having a cavity defined by an interior surface of the molded package structure, the optical path extending in the cavity between the first and second circuit structures.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Applicant: Texas Instruments IncorporatedInventors: Barry Jon Male, Benjamin Cook, Robert Alan Neidorff, Steve Kummerl