Abstract: The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The network interface offloads IPsec processing from the host processor. According to the invention, the security system includes two processors for encrypting and authenticating the outgoing data. Outgoing data packets are sent alternately to one or the other processor, whereby transmission processing can be accelerated relative to receive processing.

Abstract: A network interface system includes a memory system for managing data obtained via a system bus that supports split transactions. The memory system comprises a first memory for storing outgoing assembled data frames and associated control information prior to transfer of the outgoing data to the network, and an assembly memory that stores unassembled outgoing data from the bus. A memory control system stores the control information associated with pending bus read requests and also transfers outgoing data from the assembly memory to the first memory when all the outgoing data for a corresponding read request has been assembled.

Abstract: Network interface systems are disclosed comprising a bus interface system, a media access control system, a memory system, a security system for selectively encrypting outgoing data and decrypting incoming data, a checksum system for generating and verifying checksum values, and a segmentation system for selectively segmenting outgoing data, where the network interface system may be fabricated as a single integrated circuit chip. Methods are also provided for interfacing a host system with a network, in which checksum information is obtained from the host system, which is used to generate checksum values for outgoing data while the data is being stored in a network interface memory system.

Abstract: The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, a memory system, and a security system. The security system is coupled to the memory system and is adapted to selectively perform security processing on incoming and outgoing data. For at least one of receive or transmit processing, the security system comprises one or more encryption pipelines and at least two sets of one or more authentication pipelines. The encryption pipelines are adapted to perform one or more encryption or decryption algorithms. The authentication pipelines are adapted to perform one or more authentication algorithms. The security system is configured to selectively process frames through the encryption pipelines and then through the two sets of authentication pipelines. The system toggles whereby successive frames alternate between the two sets of authentication pipelines.

Abstract: Methods and systems are provided for reducing partial cache writes in transferring incoming data status entries from a peripheral device to a host. The methods comprise determining a lower limit on a number of available incoming data status entry positions in an incoming data status ring in the host system memory, and selectively transferring a current incoming data status entry to the host system memory using a full cache line write if the lower limit is greater than or equal to a first value. Peripheral systems are provided for providing an interface between a host computer and an external device or network, which comprise a descriptor management system adapted to determine a lower limit on a number of available incoming data status entry positions in an incoming data status ring in a host system memory, and to selectively transfer a current incoming data status entry to the host system memory using a full cache line write if the lower limit is greater than or equal to a first value.

Abstract: The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The network interface offloads IPsec processing from the host processor. According to the invention, the security system includes two processors for encrypting and authenticating the outgoing data. Outgoing data packets are sent alternately to one or the other processor, whereby transmission processing can be accelerated relative to receive processing.

Abstract: The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The network interface offloads IPsec processing from the host processor. According to the invention, the security system includes two processors for encrypting and authenticating the outgoing data. Outgoing data packets are sent alternately to one or the other processor, whereby transmission processing can be accelerated relative to receive processing.

Abstract: A security association architecture system of the present invention facilitates network data transfer by providing an internal portion of a security association database that can be quickly accessed to obtain security associations as well as an external component that stores the complete security association database. As a result, at least some security associations for incoming received frames and outgoing transmitted frames can be obtained from the internal portion located on a network interface device without accessing system memory, a host computer, and the like in order to obtain the security associations to perform security processing.

Abstract: Soda lime silica float glass in ribbon form is produced at reduced cost by replacing at least part of the soda ash conventionally used as a source of sodium fluxing agent by calcined trona ore. The invention may use calcined trona ore from the deposits in the Green River Valley area of Wyoming, USA.

Abstract: The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The security system is operative to selectively authenticate incoming and outgoing data. The security system includes a pipeline that masks mutable fields from incoming data prior to authentication.

Abstract: One aspect of the invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The security system selectively perform security processing on data incoming from the network based on security associations stored in a memory external to the network interface system, typically a host system memory. The security association for any given frame, when available, is fetched from the external memory after the frame begins to arrive in the network interface system based in part on information contained in the frame. Preferably, the fetch begins before the frame is fully received and the security association is queued whereby security processing can begin without having to wait for the security association to be fetched.

Abstract: A network device that controls the communication of data frames between stations includes ports that receive data frames from the stations and transmit the data frames. A number of the ports may be configured as a trunk and at least one of the ports in the trunk may be configured to transmit data frames at a higher speed than the other ports. The network device further includes data frame processing logic that identifies ports on which to transmit the received data frames. The data frame processing logic also determines whether the identified port is part of the trunk. When the port is part of the trunk, the data frame processing logic determines an appropriate port on which to transmit the data frame. The data frame processing logic may determine the appropriate port based on the priority associated with the received data frame so that higher priority data frames are transmitted on higher speed ports.

Abstract: An automatic flow control mechanism that supports two modes of automatic flow control is provided in a network interface. In the first flow control mode, the network interface periodically compares the number of available receive descriptors with low and high threshold values. When the number of available receive descriptors falls below the low threshold value, the network interface sends a PAUSE frame requesting the link partner to suspend its transmission (in a full-duplex mode), or enables the back pressure mechanism (in a half-duplex mode).

Abstract: An improved descriptor system is provided in which read pointers indicate to a host and a peripheral the next location to read from a queue of descriptors, and write pointers indicate the next location to be written in a queue. The system also allows an incoming descriptor to point to a plurality of data frames for transfer to the host processor, wherein the peripheral need not read a new descriptor each time a frame is to be transferred to the host.

Abstract: A motor vehicle having a plurality of road engaging wheels (7-10), a braking system (3, 14-18) linked to the wheels (7-10) by which a driver of the vehicle (1) may brake the vehicle, a motive means (50) linked to one or more of the wheels (7-10) by which a driver of the vehicle may control vehicle speed, and a dynamic stability control system that includes a means (12-17, 20-22, 24) for deducing the position and orientation of the vehicle system (12-17, 20-22, 24) for predicting the trajectory (TP) of the motor vehicle (1) with respect to the roadway (4) and for identifying when the predicted trajectory (TP) would place the vehicle in danger, and a wheel slip detection system (14-18, 51) for detecting loss of traction of one or more of the wheels (12-17).

Abstract: In a packet switch, such as an Ethernet switch, the network interface cards (NICs) of the switch perform processing functions relating to tags that identify packets or frames for a particular virtual local area network (VLAN) supported by the switch. Descriptors used to process the frames in the buffer memory of the switch provide tag information and tag status indicators and/or tag processing commands. Upon reception of a frame, a NIC recognizes the type of the frame as it relates to VLAN tagging. As the NIC writes the frame to a receive buffer location, it also writes a tag type indicator and any tag information read from the frame into the receive descriptor for that frame. The switch CPU creates a transmit descriptor that includes the pointer to the transmit buffer location in memory, and that descriptor includes a tag control command as well as a tag information field.

Abstract: A proxy device such as a microcontroller, coupled to the SMBus, is configured for obtaining, according to the SMBus Address Resolution Protocol (ARP) and from an Address Resolution Protocol (ARP) master, an SMBus slave address for an SMBus device. The proxy device also is configured for outputting the obtained SMBus slave address for storage by the SMBus device independent of the ARP protocol. Hence, the proxy agent enables SMBus slave addresses to be assigned in SMBus devices that lack the ability to receive an assigned SMBus address according to the SMBus ARP.

Abstract: A sequence of data blocks written onto a medium of a data storage system includes first and subsequent appended data blocks having an append point code for identifying the first appended data block location. For data blocks having a running block number or frame number, the block or frame number of the first appended data block is stored as the append point code. The appended point code identifies the most recently append point location and aids in processes, such as tracking calibration, data integrity confirmation and track positioning.

Abstract: A controller is configured for controlling a physical layer transceiver by setting the physical layer transceiver into a low-power operation. The physical layer transceiver is configured for operating at a selected data rate, from one of a high-speed data rate and a low data rate, according to an autonegotiation routine. The controller is configured for resetting the selected data rate to the low data rate in response to a low-power request, and restarting the autonegotiation for the low data rate within the physical layer transceiver. The controller responds to the low-power request based on a determined result of the autonegotiation for the low data rate. Hence, the controller overrides the physical layer transceiver, having selected the high-speed data rate based on autonegotiation, to renegotiate for the low data rate, enabling low-power operation at the low data rate with minimal complexity and no modification to the physical layer transceiver.

Abstract: An I/O device configured for accessing a system memory via a peripheral bus minimizes I/O read accesses required by a CPU, by copying an interrupt status value from its interrupt register to a prescribed location in the system memory. Once the interrupt status value is copied into system memory, the I/O device generates an interrupt to notify the CPU of an interrupt condition requiring servicing. Hence, the interrupt status value stored in system memory enables the CPU to service the interrupt based on reading the interrupt status value from system memory, eliminating the necessity of performing an I/O read operation of the interrupt register within the I/O device via a peripheral bus.