Abstract: A processor which is switchable between a first execution mode (such as a scalar mode) and a second execution mode (such as a VLIW mode) is disclosed. The processor has a first processor context when in the first execution mode and a second processor context, different from the first processor context, when in the second execution mode. The processor generates an exception when the processor attempts to change from one execution mode to the other. When the processor switches to a thread of execution which is in the first execution mode, or when the processor switches to a thread of execution which was the last thread to be in the second execution mode, only the first processor context is preserved. The processor may be arranged such that the number of threads that may be in the second execution mode at any one time is less than the total number of threads that may be active on the processor at any one time.

Abstract: A processor which is switchable between a first execution mode (such as a scalar mode) and a second execution mode (such as a VLIW mode) is disclosed. The processor has a first processor context when in the first execution mode and a second processor context, different from the first processor context, when in the second execution mode. The processor generates an exception when the processor attempts to change from one execution mode to the other. When the processor switches to a thread of execution which is in the first execution mode, or when the processor switches to a thread of execution which was the last thread to be in the second execution mode, only the first processor context is preserved. The processor may be arranged such that the number of threads that may be in the second execution mode at any one time is less than the total number of threads that may be active on the processor at any one time.

Abstract: A network interface for an asynchronous cell switched communication network includes a data input, a memory for buffering data received at the data input, and a clock signal generator for providing a clock signal having a frequency which is controlled in accordance with a fill level of the buffer memory. The clock signal is used to control a rate of transfer of data from the buffer memory. Data received at the network interface device is consumed by a buffer, typically a FIFO device. When the buffer fill level exceeds a predetermined level, the clock signal frequency is increased and conversely, when the buffer fill level drops below the predetermined level, the clock signal frequency is decreased.