Patents by Inventor Robert Allen Hood

Robert Allen Hood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6988110
    Abstract: A data management system has at least one class distinction cue associated with a class of data entities. The class distinction cue comprises data management guidance information and priority information related to the associated class of data entities. For a data entity, at run-time, a data management allocation run-time system references the class distinction cue or cues prior to conducting data management allocation or access, and, based on the priority information as compared to other priority information related to the data storage resources, selectively allocates the data storage resources and provides the operations of the storage system in the data management allocation system for the data entity.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: January 17, 2006
    Assignee: International Business Machines Corporation
    Inventors: Kenneth Wayne Boyd, Robert Charles Friske, Robert Allen Hood, Matthew Joseph Kalos, Robert Frederic Kern
  • Publication number: 20040215589
    Abstract: A data management system has at least one class distinction cue associated with a class of data entities. The class distinction cue comprises data management guidance information and priority information related to the associated class of data entities. For a data entity, at run-time, a data management allocation run-time system references the class distinction cue or cues prior to conducting data management allocation or access, and, based on the priority information as compared to other priority information related to the data storage resources, selectively allocates the data storage resources and provides the operations of the storage system in the data management allocation system for the data entity.
    Type: Application
    Filed: April 23, 2003
    Publication date: October 28, 2004
    Applicant: International Business Machines Corporation
    Inventors: Kenneth Wayne Boyd, Robert Charles Friske, Robert Allen Hood, Matthew Joseph Kalos, Robert Frederic Kern
  • Patent number: 6049449
    Abstract: A computer includes a main enclosure for housing a plurality of computer components. A subenclosure or card cage for housing a planar circuit board, including a CPU means, and at least one accessory board may be removably secured within the main enclosure, wherein the subenclosure, planar circuit board, and accessory circuit board may be selectively removed from the main enclosure as a unit. A connection means is provided to releasably electrically connect at least the planar circuit board to one of the computer components housed within the main enclosure.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: April 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: William Vincent Cranston, III, Robert Allen Hood, Frederick Charles Yentz, Jose Platon Basco
  • Patent number: 5708563
    Abstract: A computer includes a main enclosure for housing a plurality of computer components. A subenclosure or card cage for housing a planar circuit board, including a CPU, and at least one accessory board may be removably secured within the main enclosure, wherein the subenclosure, planar circuit board, and accessory circuit board may be selectively removed from the main enclosure as a unit. A connection device is provided to releasably electrically connect at least the planar circuit board to one of the computer components housed within the main enclosure.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: January 13, 1998
    Assignee: International Business Machines Corporation
    Inventors: William Vincent Cranston, III, Robert Allen Hood, Frederick Charles Yentz, Jose Platon Basco
  • Patent number: 4103329
    Abstract: Hardware facilities are described whereby the handling of data represented by variable length fields of bits may be made faster, use less storage and be less prone to errors in programming. The bit fields are handled independently of the natural storage addressing elements and boundaries. Data may be packed into main storage with the highest efficiency, and manipulated with a fast and efficient hardware instruction set.
    Type: Grant
    Filed: December 28, 1976
    Date of Patent: July 25, 1978
    Assignee: International Business Machines Corporation
    Inventors: Michael Ian Davis, Robert Allen Hood, Gary Wayne Mayes
  • Patent number: 4050060
    Abstract: The disclosure describes equate operand spaces (EOS) control over the addressabilities accessed by means of different address keys in an address key register (AKR) in a processor. Executing instructions, and their source and sink type operands may have different address keys in the AKR, and therefore different addressabilities. When enabled, the EOS control forces each source operand fetch to occur within the sink operand addressability specified in the AKR, even though the AKR explicitly contains a different addressability for source operands. When the EOS feature is disabled, the source operand addressability contained in the AKR is used when fetching source operands. An EOS field in the AKR stores whether the EOS state is enabled or disabled in the processor.
    Type: Grant
    Filed: April 30, 1976
    Date of Patent: September 20, 1977
    Assignee: International Business Machines Corporation
    Inventors: Richard Eugene Birney, Robert Allen Hood
  • Patent number: 4042913
    Abstract: The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.
    Type: Grant
    Filed: April 30, 1976
    Date of Patent: August 16, 1977
    Assignee: International Business Machines Corporation
    Inventors: Richard Eugene Birney, Michael Ian Davis, Lynn Allan Graybiel, Robert Allen Hood, Samuel Kahn, William Steese Osborne
  • Patent number: 4037215
    Abstract: Active address keys (AAK) are translated into respective addressabilities in physical main memory. Each addressability comprises one or more physical blocks which may be scattered in the main memory. Each address key represents the assigned addressability in main memory for a logical address space. Plural key register sections may be loaded with the same or different address keys. For each storage access request, received from a processor or I/O channel, AAK select circuits outgate to the translator the key in the key register section corresponding to the type of the current storage access request to determine the addressability available to the access request. Each address key identifies a particular stack of one or more segmentation registers. Each segmentation register can be assigned the address of any segment (i.e. a block of contiguous physical addresses located anywhere in the main memory). Each segmentation register also has validity and read-only flag bits for its assigned block.
    Type: Grant
    Filed: April 30, 1976
    Date of Patent: July 19, 1977
    Assignee: International Business Machines Corporation
    Inventors: Richard Eugene Birney, Michael Ian Davis, Robert Allen Hood, Lynn Allan Graybiel, Samuel Kahn, William Steese Osborne
  • Patent number: 4037214
    Abstract: A plurality of key register sections in a processor respectively associated with different machine-sensed types of accesses to a main storage of a computer system. A processor address key register (AKR) includes the following sections: (1) a section associated with an instruction-fetch type access, (2) a section associated with a source-operand fetch type access, and (3) a section associated with a sink-operand store/fetch type access. Other key register sections may be associated with respective sub-channel store/fetch type accesses. Circuits are provided which sense the different access types to select and outgate a key contained in the corresponding key register section.The values of the keys are associated with different addressabilities (i.e. address spaces). Each different key value is associated with a different stack of translation registers for containing the block addresses in real storage currently assigned to the respective addressabilities.
    Type: Grant
    Filed: April 30, 1976
    Date of Patent: July 19, 1977
    Assignee: International Business Machines Corporation
    Inventors: Richard Eugene Birney, Michael Ian Davis, Robert Allen Hood
  • Patent number: 4035779
    Abstract: System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR).The mode controls are provided by bits in a system register called a level status register (LSR), which include an APM bit, and a supervisor state bit. The largest supervisor addressability is obtained when both the APM and supervisor state bits are set on, which permits execution of a supervisor program which can access user data and programs. In more detail, each instruction fetch must be in the supervisor key area, identified by a predetermined supervisor key value which is not in the UKR, while each operand of the fetched supervisor instruction is accessed in the user key area identified by the current key in the UKR. The supervisor is not permitted to access any user area which does not have its key in the UKR. Thus, the supervisor can be prevented from having addressability over part or all of the main memory.
    Type: Grant
    Filed: April 30, 1976
    Date of Patent: July 12, 1977
    Assignee: International Business Machines Corporation
    Inventors: Richard Eugene Birney, Michael Ian Davis, Robert Allen Hood, Thomas Stephen McDermott, Larry Edward Wise