Abstract: A multi-core processing chip where the last-level cache functionality is implemented by multiple last-level caches (a.k.a. cache slices) that are physically and logically distributed. The hash function used by the processors on the chip is changed according to which of last-level caches are active (e.g., ‘on’) and which are in a lower power consumption mode (e.g., ‘off’.) Thus, a first hash function is used to distribute accesses (i.e., reads and writes of data blocks) to all of the last-level caches when, for example, all of the last-level caches are ‘on.’ A second hash function is used to distribute accesses to the appropriate subset of the last-level caches when, for example, some of the last-level caches are ‘off.’ The chip controls the power consumption by turning on and off cache slices based on power states, and consequently dynamically switches among at least two hash functions.

Abstract: A circuit arrangement, program product and method are provided for resetting a dynamically grown Accelerated Data Structure (ADS) used in image processing in which an ADS is initialized by reusing the root node of a prior ADS and resetting at least one node in the prior ADS to break a link between the reset node and a linked-to node in the prior ADS. By doing so, the memory allocated to the prior ADS may be reused for the new ADS, without having to clear or wipe out all of the allocated memory. In addition, in some instances, given the similarity of many image frames, often some or all of the node structure of a prior ADS may be reused for a new ADS, requiring only the contents of nodes to be cleared, instead of having to clear out all of the nodes in the prior ADS. As a result, the processing overhead associated with initializing a new ADS can be significantly reduced.

Abstract: A system that uses a write-invalidate protocol has at least two types of stores. A first type of store operation uses a write-back policy resulting in snoops for copies of the cache line at lower cache levels. A second type of store operation writes, using a coherent write-through policy, directly to the last-level cache without snooping the lower cache levels. By storing directly to the coherence point, where cache coherence is enforced, for the coherent write-through operations, snoop transactions and responses are not exchanged with the other caches. A memory order buffer at the last-level cache ensures proper ordering of stores/loads sent directly to the last-level cache.

Abstract: An interrupt controller includes a fabric slave that can receive MMIO operation requests, a plurality of output interrupt lines, a plurality of interrupt registers with each interrupt register corresponding to an output interrupt line, a MMIO routing circuit in communication with the fabric slave and the interrupt registers, a plurality of input interrupt lines for receiving line interrupts, and a line interrupt routing circuit in communication with the input interrupt lines and the interrupt registers. The interrupt registers store data for an interrupt that serves as an indication of the source of the interrupt and/or what task(s) need to be done for the interrupt.

Abstract: Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., a local cache) are described. The pixel data may derive from an image capturing device (e.g., a color camera or a depth camera) in which individual pixel values are not a multiple of eight bits. In some embodiments, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one example, the DMA engine may be configured to identify and label one or more pixels as being within a particular range of pixel values and/or the DMA engine may be configured to label pixels as belonging to one or more pixel groups based on their pixel values.

Abstract: A timing control system includes one or more device processors operatively coupled to one or more devices, a counter connected to the device processor(s), and a plurality of timing registers operatively coupled to the counter, each of the timing registers configured to store a value indicating a time at which an event is to be initiated at a corresponding one of the device(s). The system also includes a pulse generator operatively coupled to the counter and the timing registers, the pulse generator configured to generate one or more associated general-purpose input/output (GPIO) output signals, and send to each of the one or more devices an associated GPIO output signal to initiate the event at a plurality of the one or more devices in coordination with one another or to initiate the event at one of the one or more devices in coordination with another event at that device.

Abstract: A timing control system includes one or more device processors operatively coupled to one or more devices, a counter connected to the device processor(s), and a plurality of timing registers operatively coupled to the counter, each of the timing registers configured to store a value indicating a time at which an event is to be initiated at a corresponding one of the device(s). The system also includes a pulse generator operatively coupled to the counter and the timing registers, the pulse generator configured to generate one or more associated general-purpose input/output (GPIO) output signals, and send to each of the one or more devices an associated GPIO output signal to initiate the event at a plurality of the one or more devices in coordination with one another or to initiate the event at one of the one or more devices in coordination with another event at that device.

Abstract: An interrupt controller includes a fabric slave that can receive MMIO operation requests, a plurality of output interrupt lines, a plurality of interrupt registers with each interrupt register corresponding to an output interrupt line, a MMIO routing circuit in communication with the fabric slave and the interrupt registers, a plurality of input interrupt lines for receiving line interrupts, and a line interrupt routing circuit in communication with the input interrupt lines and the interrupt registers. The interrupt registers store data for an interrupt that serves as an indication of the source of the interrupt and/or what task(s) need to be done for the interrupt.

Abstract: A timing control system includes one or more device processors operatively coupled to one or more devices, a counter connected to the device processor(s), and a plurality of timing registers operatively coupled to the counter, each of the timing registers configured to store a value indicating a time at which an event is to be initiated at a corresponding one of the device(s). The system also includes a pulse generator operatively coupled to the counter and the timing registers, the pulse generator configured to generate one or more associated general-purpose input/output (GPIO) output signals, and send to each of the one or more devices an associated GPIO output signal to initiate the event at a plurality of the one or more devices in coordination with one another or to initiate the event at one of the one or more devices in coordination with another event at that device.

Abstract: Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., a local cache) are described. The pixel data may derive from an image capturing device (e.g., a color camera or a depth camera) in which individual pixel values are not a multiple of eight bits. In some embodiments, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one example, the DMA engine may be configured to identify and label one or more pixels as being within a particular range of pixel values and/or the DMA engine may be configured to label pixels as belonging to one or more pixel groups based on their pixel values.

Abstract: Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., an SRAM) are described. The pixel data may derive from a color camera or a depth camera in which individual pixel values are not a multiple of eight bits. In some cases, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one embodiment, the DMA engine may be configured to determine whether one or more pixels corresponding with the pixel data may be invalidated or skipped based on a minimum pixel value threshold and a maximum pixel value threshold and to embed pixel skipping information within unused bits of the pixel data.

Abstract: Embodiments are disclosed for a method of executing instructions in a processing core of a microprocessor. In one embodiment, the method comprises, in a first clock domain, receiving an input from a second clock domain external to the first clock domain, the input comprising an indication from the second clock domain regarding whether to execute an instruction in the first clock domain. The method further comprises synchronizing the input from the second clock domain with the first clock domain, if the instruction is a predicatable instruction and the indication matches a predicate condition that indicates not to perform the instruction, then not performing the instruction, and otherwise performing the instruction.

Abstract: By employing a two-tier load balancing scheme, embodiments of the present invention may reduce the overhead of shared resource management, while increasing the potential aggregate throughput of a thread pool. As a result, the techniques presented herein may lead to increased performance in many computing environments, such as graphics intensive gaming.

Abstract: By mapping leaf nodes of a spatial index to processing elements, efficient distribution of workload in an image processing system may be achieved. In addition, processing elements may use a thread table to redistribute workload from processing elements which are experiencing an increased workload to processing elements which may be idle. Furthermore, the workload experienced by processing elements may be monitored in order to determine if workload is balanced. Periodically the leaf nodes for which processing elements are responsible may be remapped in response to a detected imbalance in workload. By monitoring the workload experienced by the processing elements and remapping leaf nodes to different processing elements in response to unbalanced workload, efficient distribution of workload may be maintained. Efficient distribution of workload may improve the performance of the image processing system.

Abstract: A circuit arrangement, program product and circuit arrangement render stereoscopic images in a multithreaded rendering software pipeline using first and second rendering channels respectively configured to render left and right views for the stereoscopic image. Separate transformations are applied to received vertex data to generate transformed vertex data for use by each of the first and second rendering channels in rendering the left and right views for the stereoscopic image.

Abstract: A computer-implemented method includes initializing a driver associated with an input/output adapter in response to receiving an initialize driver request from a client application. The computer-implemented method includes initializing the input/output adapter to enable adapter capabilities of the input/output adapter to be determined. The computer-implemented method also includes determining the adapter capabilities of the input/output adapter. The computer-implemented method further includes determining slot capabilities of a slot associated with the input/output adapter. The computer-implemented method also includes setting configurable capabilities of the input/output adapter based on the adapter capabilities and the slot capabilities.

Abstract: A circuit arrangement, program product and method stream level of detail components between hardware threads in a multithreaded circuit arrangement to perform physics collision detection. Typically, a master hardware thread, e.g., a component loader hardware thread, is used to retrieve level of detail data for an object from a memory and stream the data to one or more slave hardware threads, e.g., collision detection hardware threads, to perform the actual collision detection. Because the slave hardware threads receive the level of detail data from the master thread, typically the slave hardware threads are not required to load the data from the memory, thereby reducing memory bandwidth requirements and accelerating performance.

Abstract: A method, program product and system for conducting a ray tracing operation where the rendering compute requirement is reduced or otherwise adjusted in response to a changing vantage point. Aspects may update or reuse an acceleration data structure between frames in response to the changing vantage point. Tree and image construction quality may be adjusted in response to rapid changes in the camera perspective. Alternatively or additionally, tree building cycles may be skipped. All or some of the tree structure may be built in intervals, e.g., after a preset number of frames. More geometric image data may be added per leaf node in the tree in response to an increase in the rate of change. The quality of the rendering algorithm may additionally be reduced. A ray tracing algorithm may decrease the depth of recursion, and generate fewer cast and secondary rays. The ray tracer may further reduce the quality of soft shadows, resolution and global illumination samples, among other quality parameters.

Abstract: A multithreaded rendering software pipeline architecture utilizes a rolling context data structure to store multiple contexts that are associated with different image elements that are being processed in the software pipeline. Each context stores state data for a particular image element, and the association of each image element with a context is maintained as the image element is passed from stage to stage of the software pipeline, thus ensuring that the state used by the different stages of the software pipeline when processing the image element remains coherent irrespective of state changes made for other image elements being processed by the software pipeline. Multiple image elements may therefore be processed concurrently by the software pipeline, and often without regard for synchronization or serialization of state changes that affect only certain image elements.

Abstract: According to embodiments of the invention, a data structure may be created which may be used by both a ray tracing unit and by a rendering engine. The data structure may have an initial or upper portion representing bounding volumes which partition a three-dimensional scene and a second or lower portion representing objects within the three-dimensional scene. The integrated acceleration data structure may be used by a rendering engine to render a two-dimensional image from a three-dimensional scene, and by a ray tracing unit to perform intersection tests.