Patents by Inventor Robert Allinger
Robert Allinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11314642Abstract: A method for updating a memory, which comprises several blocks, wherein each of the several blocks comprises multi-level cells and is operable in an MLC-mode or in a SLC-mode, wherein each multi-level cell may store more than one bit, wherein the method includes for each block to be updated: (a) copying the content of the block to a buffer block; (b) erasing the block; (c) writing the content of the block from the buffer block and an updated content for this block to this block, utilizing the capability of the block to be operated in the MLC-mode; (d) copying the updated content of the block to the buffer block; (e) erasing the block; and (f) writing the updated content from the buffer block to the block, utilizing the capability of the block to be operated in the SLC-mode. Also, therefore is a corresponding device.Type: GrantFiled: August 8, 2018Date of Patent: April 26, 2022Assignee: Infineon Technologies AGInventors: Thomas Kern, Robert Allinger, Robert Strenz
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Publication number: 20190057031Abstract: A method for updating a memory, which comprises several blocks, wherein each of the several blocks comprises multi-level cells and is operable in an MLC-mode or in a SLC-mode, wherein each multi-level cell may store more than one bit, wherein the method includes for each block to be updated: (a) copying the content of the block to a buffer block; (b) erasing the block; (c) writing the content of the block from the buffer block and an updated content for this block to this block, utilizing the capability of the block to be operated in the MLC-mode; (d) copying the updated content of the block to the buffer block; (e) erasing the block; and (f) writing the updated content from the buffer block to the block, utilizing the capability of the block to be operated in the SLC-mode. Also, therefore is a corresponding device.Type: ApplicationFiled: August 8, 2018Publication date: February 21, 2019Inventors: Thomas Kern, Robert Allinger, Robert Strenz
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Patent number: 9887006Abstract: A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line, wherein the first and second resistive elements are coupled between different metal layers; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.Type: GrantFiled: October 24, 2016Date of Patent: February 6, 2018Assignee: Infineon Technologies AGInventors: Robert Strenz, Robert Allinger
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Patent number: 9583444Abstract: A method for applying a magnetic shielding layer to a substrate is provided, wherein a first magnetic shielding layer is adhered to a first surface of the substrate. A first film layer is adhered to the first magnetic shielding layer and the first magnetic shielding layer is more adherent to the first surface than the film layer to the first magnetic shielding layer.Type: GrantFiled: August 20, 2013Date of Patent: February 28, 2017Assignee: Infineon Technologies AGInventors: Christian Peters, Robert Allinger, Klaus Knobloch, Snezana Jenei
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Patent number: 9564403Abstract: A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks.Type: GrantFiled: September 27, 2013Date of Patent: February 7, 2017Assignee: Infineon Technologies AGInventors: Robert Allinger, Karl Hofmann, Klaus Knobloch, Robert Strenz
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Patent number: 9502468Abstract: A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.Type: GrantFiled: March 6, 2014Date of Patent: November 22, 2016Assignee: Infineon Technologies AGInventors: Robert Strenz, Robert Allinger
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Patent number: 9331059Abstract: In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.Type: GrantFiled: December 10, 2013Date of Patent: May 3, 2016Assignee: INFINEON TECHNOLOGIES AGInventors: Robert Allinger, Gottfried Beer, Juergen Hoegerl
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Publication number: 20150255509Abstract: A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.Type: ApplicationFiled: March 6, 2014Publication date: September 10, 2015Applicant: Infineon Technologies AGInventors: Robert STRENZ, Robert ALLINGER
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Publication number: 20150162318Abstract: In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.Type: ApplicationFiled: December 10, 2013Publication date: June 11, 2015Applicant: Infineon Technologies AGInventors: Robert Allinger, Gottfried Beer, Juergen Hoegerl
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Publication number: 20150091109Abstract: A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: Infineon Technologies AGInventors: Robert Allinger, Karl Hofmann, Klaus Knobloch, Robert Strenz
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Publication number: 20150054102Abstract: A method for applying a magnetic shielding layer to a substrate is provided, wherein a first magnetic shielding layer is adhered to a first surface of the substrate. A first film layer is adhered to the first magnetic shielding layer and the first magnetic shielding layer is more adherent to the first surface than the film layer to the first magnetic shielding layer.Type: ApplicationFiled: August 20, 2013Publication date: February 26, 2015Inventors: Christian Peters, Robert Allinger, Klaus Knobloch, Snezana Jenei
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Patent number: 6892937Abstract: A method for operating a multistage counter in only one counting direction is described. The counting value of a single-stage auxiliary counter that can be changed in only one counting direction is changed in predetermined counting values of the multistage counter. The respective counting value states of the multistage counter and of the single-stage auxiliary counter are registered. First authenticity data is generated by logically linking the counting value of the auxiliary counter to supplementary data.Type: GrantFiled: May 29, 2002Date of Patent: May 17, 2005Assignee: Infineon Technologies AGInventors: Robert Allinger, Wolfgang Pockrandt
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Patent number: 6698652Abstract: A method of operating a multistage counter in only one counting direction includes the step of changing a counter reading of a single-stage auxiliary counter at given counter readings of the multistage counter. The single-stage auxiliary counter and the multistage counter can only be changed in one counting direction. Respective counter readings of the multistage counter and of the single-stage auxiliary counter are registered. Values of the respective counter readings of the single-stage auxiliary counter and of the multistage counter are compared with one another, and an indicator signal is generated based on a comparison result determined in the comparing step.Type: GrantFiled: November 28, 2000Date of Patent: March 2, 2004Assignee: Infineon Technologies AGInventors: Robert Allinger, Robert Hollfelder, Wolfgang Pockrandt, Armin Wedel
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Patent number: 6646503Abstract: A circuit configuration for detecting a functional disturbance has a first and a second differential amplifier. The outputs of the differential amplifiers are connected to the inputs of a gate. One input of the differential amplifiers is in each case connected to a reference potential terminal. The respective other input of the first and second differential amplifiers is connected to a monitoring means, which responds in the event of a change in the supply voltage at a supply potential terminal of the circuit configuration.Type: GrantFiled: November 18, 2002Date of Patent: November 11, 2003Assignee: Infineon Technologies AGInventors: Robert Allinger, Siegfried Tscheternigg
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Publication number: 20030080812Abstract: A circuit configuration for detecting a functional disturbance has a first and a second differential amplifier. The outputs of the differential amplifiers are connected to the inputs of a gate. One input of the differential amplifiers is in each case connected to a reference potential terminal. The respective other input of the first and second differential amplifiers is connected to a monitoring means, which responds in the event of a change in the supply voltage at a supply potential terminal of the circuit configuration.Type: ApplicationFiled: November 18, 2002Publication date: May 1, 2003Inventors: Robert Allinger, Siegfried Tscheternigg
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Publication number: 20020191733Abstract: A method for operating a multistage counter in only one counting direction is described. The counting value of a single-stage auxiliary counter that can be changed in only one counting direction is changed in predetermined counting values of the multistage counter. The respective counting value states of the multistage counter and of the single-stage auxiliary counter are registered. First authenticity data is generated by logically linking the counting value of the auxiliary counter to supplementary data.Type: ApplicationFiled: May 29, 2002Publication date: December 19, 2002Inventors: Robert Allinger, Wolfgang Pockrandt
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Publication number: 20020089890Abstract: In order to shorten an access time and thus to shorten the entire data processing time, a sector size of a memory device is adapted to respective applications. Each application is assigned a respective sector. The access right is checked only once for each application.Type: ApplicationFiled: December 24, 2001Publication date: July 11, 2002Inventors: Heiko Fibranz, Franz-Josef Brucklmayr, Robert Reiner, Robert Allinger, Klaus Klosa, Robert Hollfelder, Walter Kargl
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Patent number: 6392259Abstract: A semiconductor chip with a surface covering includes circuits which are produced in at least one layer of a semiconductor substrate and disposed in at least one group. Supply and signal lines extend in at least one interconnect plane over at least one circuit group and have a maximum width so that a distance between each two lines is at a minimum.Type: GrantFiled: August 19, 1999Date of Patent: May 21, 2002Assignee: Siemens AktiengesellschaftInventors: Robert Allinger, Wolfgang Pockrandt