Patents by Inventor Robert Alsop
Robert Alsop has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947487Abstract: Methods and systems are disclosed for performing dataflow execution by an accelerated processing unit (APU). Techniques disclosed include decoding information from one or more dataflow instructions. The decoded information is associated with dataflow execution of a computational task. Techniques disclosed further include configuring, based on the decoded information, dataflow circuitry, and, then, executing the dataflow execution of the computational task using the dataflow circuitry.Type: GrantFiled: June 28, 2022Date of Patent: April 2, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Johnathan Robert Alsop, Karthik Ramu Sangaiah, Anthony T. Gutierrez
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Publication number: 20240103730Abstract: In accordance with described techniques for reduction of parallel memory operation messages, a computing system or computing device includes a memory system that receives memory operation messages. A shared response component in the memory system receives responses to the memory operation messages, and identifies a set of the responses that are coalesceable. The shared response component then coalesces the set of the responses into a combined message for communication completion through a communication path in the memory system.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Johnathan Robert Alsop, Shaizeen Dilawarhusen Aga, Mohamed Assem Abd ElMohsen Ibrahim
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Publication number: 20240103763Abstract: In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.Type: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Mahzabeen Islam, Shaizeen Dilawarhusen Aga, Johnathan Robert Alsop, MOHAMED ASSEM ABD ELMOHSEN IBRAHIM, Nuwan S Jayasena
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Publication number: 20240106782Abstract: In accordance with described techniques for filtered responses to memory operation messages, a computing system or computing device includes a memory system that receives messages. A filter component in the memory system receives the responses to the memory operation messages, and filters one or more of the responses based on a filterable condition. A tracking logic component tracks the one or more responses as filtered responses for communication completion.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Johnathan Robert Alsop, Shaizeen Dilawarhusen Aga, MOHAMED ASSEM ABD ELMOHSEN IBRAHIM
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Publication number: 20240103745Abstract: A memory controller coupled to a memory module receives both processing-in-memory (PIM) requests and memory requests from a host (e.g., a host processor). The memory controller issues PIM requests to one group of memory banks and concurrently issues memory requests to one or more other groups of memory banks. Accordingly, memory requests are performed on groups of memory banks that would otherwise be idle while PIM requests are performed on the one group of memory banks. Optionally, the memory controller coupled to the memory module also takes various actions when switching between operating in a PIM mode and a non-processing-in-memory mode to reduce or hide overhead when switching between the two modes.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Niti Madan, Johnathan Robert Alsop, Alexandru Dutu, Mahzabeen Islam, Yasuko Eckert, Nuwan S Jayasena
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Publication number: 20240069915Abstract: A virtual padding unit provides a virtual padded data structure (e.g., virtually padded matrix) that provides output values for a padded data structure without storing all of the padding elements in memory. When the virtual padding unit receives a virtual memory address of a location in the virtual padded data structure, the virtual padding unit checks whether the location is a non-padded location in the virtual padded data structure or a padded location in the virtual padded data structure. If the location is a padded location in the virtual padded data structure, the virtual padding unit outputs a padding value rather than a value stored in the virtual padded data structure. If the location is a non-padded location in the virtual padded data structure, a value stored at the location is output.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Meysam Taassori, Shaizeen Dilawarhusen Aga, Mohamed Assem Abd ElMohsen Ibrahim, Johnathan Robert Alsop
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Publication number: 20230418782Abstract: Methods and systems are disclosed for performing dataflow execution by an accelerated processing unit (APU). Techniques disclosed include decoding information from one or more dataflow instructions. The decoded information is associated with dataflow execution of a computational task. Techniques disclosed further include configuring, based on the decoded information, dataflow circuitry, and, then, executing the dataflow execution of the computational task using the dataflow circuitry.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Johnathan Robert Alsop, Karthik Ramu Sangaiah, Anthony T. Gutierrez
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Patent number: 9670623Abstract: A bonded fastener for a railway rail comprising: top and bottom generally horizontal plates bonded and separated by an insulating material wherein the top plate defines a rail bed; a plurality of clip housings wherein each clip housing houses part of a hold-down clip for attaching the rail to the bonded fastener; a plurality of anchor assembly areas wherein each anchor assembly area defines an opening through the bonded fastener for receiving an attachment device for attaching the fastener to a supporting surface; and one or more generally vertical barriers comprising part of the bonded fastener. Further, a first generally horizontal barrier may extend from the bonded fastener underneath each of the clip housings, and a second generally horizontal barrier may extend from the rail bed underneath the rail on each side of the bonded fastener.Type: GrantFiled: September 4, 2014Date of Patent: June 6, 2017Assignee: L B Foster CompanyInventors: Korhan Ciloglu, Robert Alsop, Pete Frye, Michael O'Connell
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Patent number: 9004372Abstract: A bonded, direct fixation fastener as supportive structure for a rail on a railroad tie or bed comprising: a rail plate, wherein the rail plate has a generally horizontal center portion having a lower face and an upper face and defining a rail plate horizontal plane, and wherein the rail plate center portion extends at a first angle from opposing sides as rail plate tongues above the rail plate horizontal plane, the rail plate having a rail securing device; a bed plate comprising a generally horizontal center portion, an upper bed plate face defining a bed plate horizontal plane, and a pair of opposing bed plate tongues extending from opposing sides of the bed plate horizontal center portion disposed at a second angle above the bed plate horizontal plane; a horizontal elastomeric portion of relatively lower durometer hardness encapsulating at least a portion of the bed plate and at least a portion of the rail plate; and vertical elastomeric portions of relatively higher durometer hardness encapsulating at leaType: GrantFiled: August 29, 2012Date of Patent: April 14, 2015Assignee: L. B. Foster CompanyInventors: Robert Alsop, Korhan Ciloglu, Hakan Eksi, Michael O'Connell
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Patent number: 8985476Abstract: An assembly to hold a rail boot to a rail during embedded track construction comprising: a cover having a bottom surface, a first portion of the bottom surface generally conforming to a length of a top surface of a rail head; the bottom surface having a second portion defining a convex shape adjacent to and generally parallel to the length of the top surface of the rail head; the bottom surface further defining a hook to engage a gauge side of the rail boot; and a clip having first and second ends, wherein the first end engages a gauge side of the cover; and the second end engages a field side of the cover and/or the rail boot.Type: GrantFiled: April 5, 2012Date of Patent: March 24, 2015Assignee: L. B. Foster CompanyInventors: Michael O'Connell, Robert Alsop
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Publication number: 20150060561Abstract: A bonded fastener for a railway rail comprising: top and bottom generally horizontal plates bonded and separated by an insulating material wherein the top plate defines a rail bed; a plurality of clip housings wherein each clip housing houses part of a hold-down clip for attaching the rail to the bonded fastener; a plurality of anchor assembly areas wherein each anchor assembly area defines an opening through the bonded fastener for receiving an attachment device for attaching the fastener to a supporting surface; and one or more generally vertical barriers comprising part of the bonded fastener. Further, a first generally horizontal barrier may extend from the bonded fastener underneath each of the clip housings, and a second generally horizontal barrier may extend from the rail bed underneath the rail on each side of the bonded fastener.Type: ApplicationFiled: September 4, 2014Publication date: March 5, 2015Applicant: L.B. Foster CompanyInventors: Korhan Ciloglu, Robert Alsop, Pete Frye, Michael O'Connell
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Patent number: D616791Type: GrantFiled: June 29, 2009Date of Patent: June 1, 2010Assignee: L.B. Foster CompanyInventors: Korhan Ciloglu, Hakan Eksi, Robert Alsop
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Patent number: D724490Type: GrantFiled: August 4, 2010Date of Patent: March 17, 2015Assignee: L.B. Foster CompanyInventors: Korhan Ciloglu, Michael O'Connell, Robert Alsop
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Patent number: D756844Type: GrantFiled: March 15, 2013Date of Patent: May 24, 2016Assignee: L.B. Foster CompanyInventors: Scott Almes, Robert Alsop, Korhan Ciloglu