Abstract: Random access memory (RAM) is attached to an input/output (I/O) controller of a chipset (e.g., on a motherboard). This chipset attached RAM is optionally used as part of a tiered storage solution with other tiers including, for example, nonvolatile memory (e.g., a solid state drive (SSD)) or a hard disk drive. The chipset attached RAM is separate from the system memory, allowing the chipset attached RAM to be used to speed up access to frequently used data stored in the tiered storage solution without reducing the amount of system memory available to an operating system running on the one or more processing units.

Abstract: Temporary system adjustment for component overclocking is described. In accordance with the described techniques, a processor and/or memory are operated according to first settings. During operation of the processor and/or the memory according to the first settings, a signal triggers a temporary adjustment of operation of the processor and/or the memory according to second settings. Responsive to the request, operation of the processor and/or the memory is switched to the second settings without rebooting. After a duration, operation of the processor and/or the memory is switched back to the first settings. In one or more implementations, at least one of the first settings or the second settings overclock the processor and/or the memory.

Abstract: A switch capable of on-the-fly reduction in a network is provided. The switch is equipped with a reduction engine that can be dynamically configured to perform on-the-fly reduction. As a result, the network can facilitate an efficient and scalable environment for high performance computing.

Abstract: A network interface controller (NIC) capable of performing message passing interface (MPI) list matching is provided. The NIC can include a host interface, a network interface, and a hardware list-processing engine (LPE). The host interface can couple the NIC to a host device. The network interface can couple the NIC to a network. During operation, the LPE can receive a match request and perform MPI list matching based on the received match request.

Abstract: A switch equipped with a self-managing reduction engine is provided. During operation, the reduction engine can use a timeout mechanism to manage itself in different latency-induced or error scenarios. As a result, the network can facilitate an efficient and scalable environment for high performance computing.

Abstract: A network interface controller (NIC) capable of efficient packet forwarding is provided. The NIC can be equipped with a host interface, a packet generation logic block, and a forwarding logic block. During operation, the packet generation logic block can obtain, via the host interface, a message from the host device and for a remote device. The packet generation logic block may generate a plurality of packets for the remote device from the message. The forwarding logic block can then send a first subset of packets of the plurality of packets based on ordered delivery. If a first condition is met, the forwarding logic block can send a second subset of packets of the plurality of packets based on unordered delivery. Furthermore, if a second condition is met, the forwarding logic block can send a third subset of packets of the plurality of packets based on ordered delivery.

Abstract: Package lids with carveouts configured for processor connection and alignment are described. Lid carveouts are configured to align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device. Because the lid carveouts ensure precise alignment and orientation of a cooling device relative to a package lid, the lid design enables targeted cooling of discrete portions of the lid. Lid carveouts are further configured to expose one or more connectors disposed on a surface that supports package internal components. When contacted by corresponding connectors of a cooling device, the lid carveouts enable direct connections between the package and the attached cooling device. By creating a direct connection between package components and an attached cooling device, the lid carveouts enable a high-speed connection for proactive and on-demand cooling actuation.

Abstract: A switch capable of on-the-fly reduction in a network is provided. The switch is equipped with a reduction engine that can be dynamically configured to perform on-the-fly reduction. As a result, the network can facilitate an efficient and scalable environment for high performance computing.

Abstract: Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.

Abstract: A network interface controller (NIC) capable of efficient packet forwarding is provided. The NIC can be equipped with a host interface, a packet generation logic block, and a forwarding logic block. During operation, the packet generation logic block can obtain, via the host interface, a message from the host device and for a remote device. The packet generation logic block may generate a plurality of packets for the remote device from the message. The forwarding logic block can then send a first subset of packets of the plurality of packets based on ordered delivery. If a first condition is met, the forwarding logic block can send a second subset of packets of the plurality of packets based on unordered delivery. Furthermore, if a second condition is met, the forwarding logic block can send a third subset of packets of the plurality of packets based on ordered delivery.

Abstract: Adjustable thermal management is described. Input to adjust one or more parameters for controlling thermal conditions of a component is received. Temperature measurements of a component are obtained from two or more sensors of the component. A temperature of a thermal hotspot of the component is estimated based on the temperature measurements obtained from the two or more sensors of the component and using the adjusted parameters. Operation of the component is adjusted based on the estimated temperature of the thermal hotspot.

Abstract: Task scheduling based on component margins is described. In accordance with the described techniques, a scheduler of an operating system accesses a margin table when a request to perform tasks is received. The scheduler schedules tasks on various components of a system based on margins of those components. When a request to perform a task is received, for example, the scheduler accesses the margin table and selects a component to perform the task based on the margin information included in the margin table as well as based on the task, such as whether the task benefits more from being performed fast or being performed accurately. The scheduler then schedules the task using the selected component.

Abstract: Task allocation with chipset attached memory and additional processing unit is described. In accordance with the described techniques, a computing device includes a main system and one or more sub-systems which are coupled to the main system via a chipset link. The main system includes at least a processing unit and a system memory. The one or more sub-systems each include at least a chipset attached processing unit and a chipset attached memory. Contents of the system memory are transferable to the chipset attached memory of the sub-system via the chipset link to enable the chipset attached processing unit to perform the one or more tasks using the contents from the chipset attached memory.

Abstract: A system that includes at least a system memory, a chipset link, and a chipset attached memory is powered down. A boot-up process is loaded in the chipset attached memory. The boot-up process is performed for the system, via the chipset link, by the chipset attached memory. The boot-up process includes loading one or more memory testing applications. The system memory is tested using the one or more memory testing applications loaded by the chipset attached memory.

Abstract: Dynamic range aware conversion of sensor readings is described. A system includes one or more sensors to sense conditions of a component and output sensor readings and a system manager. The system manager is configured to convert the sensor readings into condition measurements by converting the sensor readings into the condition measurements using a first transformation while operating in a first conversion mode or converting the sensor readings into the condition measurements using a second transformation while operating in a second conversion mode. The system manager then adjusts operation of the component based on the condition measurements.

Abstract: Duplicating memory content with chipset attached memory is described. In accordance with the described techniques, contents of a system memory are duplicated on a chipset attached memory over a chipset link. Memory requests are serviced using the contents of the system memory and the contents on the chipset attached memory. Servicing the memory requests includes servicing a first portion of a read request using the contents of the system memory and a second, remaining portion of the read request using the contents on the chipset attached memory. Servicing the memory requests further includes communicating a write request to the system memory and to the chipset attached memory.

Abstract: User configurable hardware settings for overclocking is described. In accordance with the described techniques, user input to adjust hardware settings for operating a processing unit in an overclocking mode is received. The user input, for example, adjusts at least one of a voltage droop threshold or a frequency adjustment of the clock rate. A voltage droop is detected while operating the processing unit in the overclocking mode. Responsive to detecting the voltage droop, a clock rate of the processing unit is adjusted based at least in part on the adjusted hardware settings.

Abstract: Automated memory overclocking is described. In accordance with the described techniques, one or more sets of overclocked memory settings of a memory are automatically selected for performance testing and stability testing of the memory. The one or more sets of the overclocked memory settings are tested for performance of the memory and a performance indication is output for each of the one or more sets of the overclocked memory settings. The one or more sets of the overclocked memory settings are tested for stability of the memory and a stability indication is output for each of the one or more sets of the overclocked memory settings. One of the one or more sets of the overclocked memory settings are selected as optimized overclocked memory settings for the memory.

Abstract: Induced signal marginality for random number generation is described. In accordance with the described techniques, a pseudorandom number is transmitted across an interface while the interface is operated with settings configured to cause instability in the interface. A random number is received as an output of the interface. The settings configured to cause instability in the interface include overclocked settings of interface operating parameters.

Abstract: Physical adjustment to system memory with chipset attached memory is described. In accordance with the described techniques, an indication for making one or more physical adjustments to system memory of a device is received. Contents of the system memory are transferred via a chipset link to a chipset attached memory. The device is operated using the contents from the chipset attached memory while the one or more physical adjustments are made to adjust the system memory. After the one or more physical adjustments, the contents are transferred back from the chipset attached memory to the adjusted system memory via the chipset link.