Abstract: A method of fabricating a silicon-based microstructure is disclosed, which involves depositing electrically conductive amorphous silicon doped with first and second dopants to produce a structure having a residual mechanical stress of less than +/=100 Mpa. The dopants can either be deposited in successive layers to produce a laminated structure with a residual mechanical stress of less than +/=100Mpa or simultaneously to produce a laminated structure having a mechanical stress of less than +/=100Mpa.

Abstract: A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a sacrificial layer over the protective layer, opening holes in the sacrificial layer and the protective layer to allow the connection of the MEM device to the electronic device, fabricating the MEM device by depositing and patterning at least one layer of amorphous silicon, and removing at least a portion of the sacrificial layer. In this way, the MEM device can be fabricated after the electronic device on the same substrate.

Abstract: A method of fabricating a silicon-based microstructure is disclosed, which involves depositing electrically conductive amorphous silicon doped with first and second dopants to produce a structure having a residual mechanical stress of less than +/=100 Mpa. The dopants can either be deposited in successive layers to produce a laminated structure with a residual mechanical stress of less than +/=100 Mpa or simultaneously to produce a laminated structure having a mechanical stress of less than +/=100 Mpa.

Abstract: A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a sacrificial layer over the protective layer, opening holes in the sacrificial layer and the protective layer to allow the connection of the MEM device to the electronic device, fabricating the MEM device by depositing and patterning at least one layer of amorphous silicon, and removing at least a portion of the sacrificial layer. In this way, the MEM device can be fabricated after the electronic device on the same substrate.

Abstract: A method of fabricating a silicon-based microstructure is disclosed, which involves depositing electrically conductive amorphous silicon doped with first and second dopants to produce a structure having a residual mechanical stress of less than +/=100 Mpa. The dopants can either be deposited in successive layers to produce a laminated structure with a residual mechanical stress of less than +/=100 Mpa or simultaneously to produce a laminated structure having a mechanical stress of less than +/=100 Mpa.

Abstract: A method of fabricating a silicon-based microstructure is disclosed, which involves depositing electrically conductive amorphous silicon doped with first and second dopants to produce a structure having a residual mechanical stress of less than +/=100 Mpa. The dopants can either be deposited in successive layers to produce a laminated structure with a residual mechanical stress of less than +/=100 Mpa or simultaneously to produce a laminated structure having a mechanical stress of less than +/=100 Mpa.

Abstract: A cavity forming formed in an encapsulation structure under a vacuum in a vacuum chamber is sealed with a capping layer. A stiff protective layer under tensile stress is deposited on the capping layer prior to venting the vacuum chamber to atmospheric pressure. The capping layer is preferably aluminum or an aluminum alloy, and the protective layer is preferably ?-TiN having a suitable high Young's modulus.

Abstract: A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a sacrificial layer over the protective layer, opening holes in the sacrificial layer and the protective layer to allow the connection of the MEM device to the electronic device, fabricating the MEM device by depositing and patterning at least one layer of amorphous silicon, and removing at least a portion of the sacrificial layer. In this way, the MEM device can be fabricated after the electronic device on the same substrate.

Abstract: A method is disclosed for evaluating an anisotropic etch in a microstructure. First a film is formed on a substrate. Next a series of holes of progressively different area and having specific geometric shapes are formed through the film. An anisotropic etch is carried out in the microstructure through the holes by relying on different etch rates in different crystal planes under known and reproducible conditions. Finally, the microstructure is inspected through the holes after the anisotropic etch to compare results from holes of different area. The method is useful in the determination of etch depth.

Abstract: In order to align a mask to a specific crystal plane in a wafer, a first mask having at least one alignment structure is deposited on the wafer surface. The alignment structure is coarsely aligned with the specific crystal plane and has an array of components that are offset relative to each other by known angles defining the degree of precision with which said mask can be finely aligned with said crystal plane. Next, an anisotropic etch is performed through the first mask to etch the alignment structure into the wafer surface. The components of the alignment structure produce different etch patterns in the wafer surface according to their relative orientation to the specific crystal plane. Finally, a second mask is formed on the wafer surface having a reference structure thereon. The reference structure on the second mask is aligned relative to an etch pattern identified as being finely aligned with the specific crystal plane.

Abstract: A cavity forming formed in an encapsulation structure under a vacuum in a vacuum chamber is sealed with a capping layer. A stiff protective layer under tensile stress is deposited on the capping layer prior to venting the vacuum chamber to atmospheric pressure. The capping layer is preferably aluminum or an aluminum alloy, and the protective layer is preferably &dgr;-TiN having a suitable high Young's modulus.

Abstract: A method is disclosed for evaluating an anisotropic etch in a microstructure. First a film is formed on a substrate. Next a series of holes of progressively different area and having specific geometric shapes are formed through the film. An anisotropic etch is carried out in the microstructure through the holes by relying on different etch rates in different crystal planes under known and reproducible conditions. Finally, the microstructure is inspected through the holes after the anisotropic etch to compare results from holes of different area. The method is useful in the determination of etch depth.

Abstract: In order to align a mask to a specific crystal plane in a wafer, a first mask having at least one alignment structure is deposited on the wafer surface. The alignment structure is coarsely aligned with the specific crystal plane and has an array of components that are offset relative to each other by known angles defining the degree of precision with which said mask can be finely aligned with said crystal plane. Next, an anisotropic etch is performed through the first mask to etch the alignment structure into the wafer surface. The components of the alignment structure produce different etch patterns in the wafer surface according to their relative orientation to the specific crystal plane. Finally, a second mask is formed on the wafer surface having a reference structure thereon. The reference structure on the second mask is aligned relative to an etch pattern identified as being finely aligned with the specific crystal plane.