Abstract: An improved method and apparatus for performing single-cycle operations (such as Viterbi decode) in digital processors is disclosed. In one aspect, the invention comprises methods for storing (“packing”) old and new metric data in memory that cooperate with a single-operand instruction adapted to perform single cycle calculations such as the Viterbi butterfly. Accordingly, such calculations can be computed effectively in software in a single cycle. In another aspect, an improved memory addressing mode is used to write back two new output results at the completion of instruction execution. The improved packing of state metrics in memory, single-operand instruction, and addressing mode can advantageously be integrated into any processor (e.g., DSP, RISC-DSP, or configurable processor) with appropriate memory. The user of such a processor may accordingly write software using the single-operand instruction to perform Viterbi decode with the efficiency comparable to a dedicated hardware implementation.

Abstract: An improved method and apparatus for performing single-cycle operations (such as Viterbi decode) in digital processors is disclosed. In one aspect, the invention comprises methods for storing (“packing”) old and new metric data in memory that cooperate with a single operand instruction adapted to perform single cycle calculations such as the Viterbi butterfly. Accordingly, such calculations can be computed effectively in software in a single cycle. In another aspect, an improved memory addressing mode is used to write back two new output results at the completion of instruction execution. The improved packing of state metrics in memory, single operand instruction, and addressing mode can advantageously be integrated into any processor (e.g., DSP, RISC-DSP, or configurable processor) with appropriate memory. The user of such a processor may accordingly write software using the single operand instruction to perform Viterbi decode with the efficiency comparable to a dedicated hardware implementation.