Abstract: The present invention provides a method and system for a contention prevention scheme which provides contention prevention during scan-based test without adversely affecting the functional timing of the path circuit. The contention prevention scheme provides a circuit which includes a path circuit gated by a contention prevention circuit (CPC) and the CPC, where the CPC allows functional operation to occur without adversely affecting the functional operation timing, provided that a time skew between two input signals to the CPC is approximately less than a difference between a time delay associated with a scan-based test logic value and a time delay associated with a functional logic value. With a contention prevention circuit tuned in this manner, a static logical value during functional mode is provided, indicating no contention, which avoids adversely affecting the functional timing of the path circuit.