Abstract: A buffered crossbar switch is provided with a buffer to port relationship that supports cells and packets of variable size. A novel scheduler is provided that allows for an efficient crossbar switch, where the relationship between the number of internal buffers is less than the number of ports squared. This allows for a switch that can be implemented that requires less buffer memory.

Abstract: An improved string switch architecture is provided having a partial shared memory. The string switch includes a plurality of input ports configured to classify incoming packets, wherein the destination output port and priority is determined at classification; a plurality of output ports, each having a string bank of memory units that compose the aggregate output queue memory for each port; a write manager configured to receive write requests and to write each packet directly to the appropriate memory location within each output port; where each output port includes an assignment block configured to receive packets originating from each input port; and a read manager configured to read data from the plurality of output ports. The write manager may be configured to write packet data received in a round robin fashion, which may be independent from the packet protocol.

Abstract: A network switch is provided that includes a bank of input switches configured to receive variable length data packets; a bank of central switches configured to receive packets from the input switches in a distributed manner; and a bank of output switches configured to receive and output variable length packets from the bank of central switches.

Abstract: A buffered crossbar switch is provided with a buffer to port relationship that supports cells and packets of variable size. A novel scheduler is provided that allows for an efficient crossbar switch, where the relationship between the number of internal buffers is less than the number of ports squared. This allows for a switch that can be implemented that requires less buffer memory.

Abstract: The apparatus for symbol boundary synchronization in one embodiment includes on the receive path of a multi-tone modem a window synchronizer, a converter and a symbol boundary component. The window synchronizer obtains windowed portions of the received datastream which includes symbols each expressed with a corresponding set of tones in a time domain. The windowed portions obtained in the training phase exhibit varying degrees of misalignment with the corresponding symbol boundaries. The window synchronizer is responsive to an alignment signal to obtain succeeding windowed portions of the incoming datastream aligned with the corresponding symbol boundaries therein. The converter couples to the window synchronizer to convert the set of tones from each windowed portion from the time domain to a frequency domain.