Abstract: A flexible capacitive coupler assembly includes a flexible dielectric substrate assembly having a front surface and a rear surface, the front surface having thereon a macroscopic metal capacitive pad. A package supports the flexible dielectric substrate. An electrical connection is made to package wiring or leads on the flexible dielectric substrate to establish electrical contact with a computer subsystem.

Abstract: A flexible capacitive coupler assembly includes a flexible dielectric substrate assembly having a front surface and a rear surface, the front surface having thereon a macroscopic metal capacitive pad. A package supports the flexible dielectric substrate. An electrical connection is made to package wiring or leads on the flexible dielectric substrate to establish electrical contact with a computer subsystem.

Abstract: An integer processing unit for a reduced instruction set computer having a plurality of registers arranged in groups referred to as register windows, each window register group including a number of input registers, a similar number of output registers, and a number of local registers, the register window groups being physically arranged so the input registers of each group are the same physical register as the output registers of the next adjacent register window group thereby forming one large interconnected ring of register window groups, an arrangement for designating the register window group presently active, and an arrangement for designating register window groups which are not available for use.

Abstract: A computer system which includes a central processing unit including a first processing unit that performs basic processing functions and a co-processing unit that performs multiple specialized processing functions concurrently with the first processing unit, an arrangement for detecting the occurrence of a function causing an exception in a result produced by the coprocessing unit, an arrangement for specifying to the first processing unit any exception in a result produced by the coprocessing unit, an arrangement for using the first processing unit to implement any function which causes an exception in a result produced by the co-processing unit, an arrangement for storing the identification of the instruction being handled by the first processing unit when a function causing any exception in a result produced by the co-processing unit occurs, and an arrangement for determing the instruction which produced the exception.

Abstract: An integer processing unit for a reduced instruction set computer having a plurality of registers arranged in groups referred to as register windows, each window register group including a number of input registers, a similar number of output registers, and a number of local registers, the register window groups being physically arranged so the input registers of each group are the same physical register as the output registers of the next adjacent register window group thereby forming one large interconnected ring of register window groups, an arrangement for designating the register window group presently active, and an arrangement for designating register window groups which are not available for use.

Abstract: An improved interface between a processor and an external cache system, having particular application for use in high speed computer systems. A cache memory for storing frequently accessed data is coupled to a cache address register (CAR). A processor generates addresses which correspond to locations of desired data in the cache, and provides these addresses to the CAR. Upon the receipt of a clock signal, the CAR couples the address to the cache memory. The processor includes a data register for receiving accessed cache data over a data bus. Data is latched into the register upon the receipt of a clock signal. Due to inherent delays associated with digital logic comprising the processor, clock signals provided by an external clock are received by the CAR prior to their receipt by the processor's data register. This delay (a fraction of a clock cycle) provides additional time to access the cache memory before the data is expected on the data bus.