Abstract: An apparatus and method for simulating timing performance of designs of digital machines which allows for the avoidance of lumping of correlation of correlation coefficients which may be significant to the slacks which may occur in a particular design. Delays of particular digital elements are derived by random selections from distributions of delay values based on correlations between different observed or otherwise reasonable distributions of relative delays of digital element pairs including pairs of senses of logic value transitions, pairs of technologies and pairs of packaging levels as an accuracy enhancement. Delay distributions are built up of weighted sums of other distributions and may be asymmetrical. Several computational enhancements disclosed include arrangements allowing reductions in paging (e.g. reduction in number of accesses to secondary memory).

Abstract: A printed circuit board for electric circuits is formed of plural layers of electrical conductors and includes through holes and vias arranged in a regular pattern along points of a grid laid out along othorgonal axes of a Cartesian coordinate system. Electrical components such as circuit chips and discrete components are to be mounted to the through holes, while the vias connect electrical conductors of different layers. Conductors of a layer are grouped together as multiple-conductor channels which are routed among the through holes and the vias to make electrical connections among the electrical components. An additional via can be entered in a central portion of a grid cell by rerouting conductors of channels in the cell through arcuate segments, thereby permitting connection between conductors of channels on different layers while preserving the original grid pattern of through holes and vias.

Abstract: An improved logic simulation machine in which non-unitary delays of logic functions being simulated are permitted and in which the delay time can be made different for low-to-high and high-to-low transitions. A plurality of basic processors are interconnected with a control processor through an inter-processor switch. The logic functions being simulated are divided among the various basic processors. The control processor provides primary input data and communicates the results computed by the basic processors with other ones of the basic processors as needed. All of the basic processors and the control processor operate in variable length work cycles. The length of a work cycle is determined by a minimum work space value among all of the logic functions to be simulated, that is, a minimum time to a next successive transition in a simulated output among all of the simulated logic functions. Further, the presence of glitches in the simulated output is detected.

Abstract: A method is provided which is applied to a logic block diagram, referred to as a block graph, which consists of a plurality of logic blocks interconnected by nets which carry logic signals between the logic blocks. The method is used to determine the characteristics of the given block graph, and more particularly to analyze the block graph to identify critical paths wherein logic signals must arrive at designated blocks at a critical time, and to determine whether the path delays of such critical paths are too long or too short. When critical paths are identified which have path delays that are too long or too short, the block graph can be redesigned to avoid such delays. The method includes three basic, broad steps each of which incorporates a plurality of subsidiary implementation steps. First, from the logic block graph, special blocks defined as storage elements because of their unique function are identified and classified as "level zero" elements.