Abstract: An improved logic simulation machine in which non-unitary delays of logic functions being simulated are permitted and in which the delay time can be made different for low-to-high and high-to-low transitions. A plurality of basic processors are interconnected with a control processor through an inter-processor switch. The logic functions being simulated are divided among the various basic processors. The control processor provides primary input data and communicates the results computed by the basic processors with other ones of the basic processors as needed. All of the basic processors and the control processor operate in variable length work cycles. The length of a work cycle is determined by a minimum work space value among all of the logic functions to be simulated, that is, a minimum time to a next successive transition in a simulated output among all of the simulated logic functions. Further, the presence of glitches in the simulated output is detected.

Abstract: A method is provided which is applied to a logic block diagram, referred to as a block graph, which consists of a plurality of logic blocks interconnected by nets which carry logic signals between the logic blocks. The method is used to determine the characteristics of the given block graph, and more particularly to analyze the block graph to identify critical paths wherein logic signals must arrive at designated blocks at a critical time, and to determine whether the path delays of such critical paths are too long or too short. When critical paths are identified which have path delays that are too long or too short, the block graph can be redesigned to avoid such delays. The method includes three basic, broad steps each of which incorporates a plurality of subsidiary implementation steps. First, from the logic block graph, special blocks defined as storage elements because of their unique function are identified and classified as "level zero" elements.