Abstract: A circuit that enhances the performance of the execution of a read-modify-write instruction type. The circuit provides hardware detection and decoding of various options specified by the instruction, and greatly improves the performance and conserves space within a micro-code control store (14). The circuit also detects anomalous cases and reports them to micro-code for special handling. The detection of the anomalous cases occurs dynamically and in parallel to instruction execution, thereby improving performance. Resulting condition codes are also provided simultaneously to the control program. The circuit operates in concert with a micro-code controlled mechanism to read a memory variable and, based on the specification of the instruction, the circuit selectively adds 1, subtracts 1, adds a 16-bit mask specified by the instruction, or subtracts the 16-bit mask, and returns the result to a central processor (12).