Patents by Inventor Robert Barrowcliff
Robert Barrowcliff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080035946Abstract: A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a Si-rich Si oxide (SRSO) film on a substrate, doped with the first rare earth element; and, annealing the rare earth element-doped SRSO film. The first target is doped with a rare earth element such as erbium (Er), ytterbium (Yb), cerium (Ce), praseodymium (Pr), or terbium (Tb). The sputtering power is in the range of about 75 to 300 watts (W). Different sputtering powers are applied to the two targets. Also, deposition can be controlled by varying the effective areas of the two targets. For example, one of the targets can be partially covered.Type: ApplicationFiled: October 9, 2007Publication date: February 14, 2008Inventors: Wei Gao, Tingkai Li, Robert Barrowcliff, Yoshi Ono, Sheng Hsu
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Publication number: 20080010707Abstract: An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.Type: ApplicationFiled: November 1, 2005Publication date: January 10, 2008Inventors: Fengyan Zhang, Robert Barrowcliff, Jong-Jan Lee, Sheng Hsu
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Publication number: 20070167008Abstract: A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.Type: ApplicationFiled: March 14, 2007Publication date: July 19, 2007Inventors: Sheng Hsu, Fengyan Zhang, Gregory Stecker, Robert Barrowcliff
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Publication number: 20070111368Abstract: A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor layer of a second dopant type, opposite of the first dopant type (i.e., p-type), overlying the first semiconductor layer; and, forming a top electrode overlying the second semiconductor layer. The first and second semiconductor layers can be a material such as a conductive polymer, a conjugated polymer with a fullerene derivative, and inorganic materials such as CdSe, CdS, Titania, or ZnO. The conductive nanowires can be a material such as IrO2, In2O3, SnO2, or indium tin oxide (ITO).Type: ApplicationFiled: November 16, 2005Publication date: May 17, 2007Inventors: Fengyan Zhang, Robert Barrowcliff, Sheng Hsu
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Patent number: 7094691Abstract: A method of forming a tungsten nitride thin film in an integrated circuit includes preparing a silicon substrate on a silicon wafer and placing the silicon wafer in a heatable chuck in a CVD vacuum chamber; placing a known quantity of a tungsten source in a variable-temperature bubbler to provide a gaseous tungsten source; setting the variable-temperature bubbler to a predetermined temperature; passing a carrier gas through the variable-temperature bubbler and carrying the gaseous tungsten source with the carrier gas into the CVD vacuum chamber; introducing a nitrogen-containing reactant gas into the CVD vacuum chamber; reacting the gaseous tungsten source and the nitrogen-containing reactant gas above the surface of the silicon wafer in a deposition process to deposit a WxNy thin film on the surface of the silicon wafer; and completing the integrated circuit containing the WxNy thin film.Type: GrantFiled: April 9, 2003Date of Patent: August 22, 2006Assignee: Sharp Laboratories of America, Inc.Inventors: Wei Pan, Robert Barrowcliff, David R. Evans, Sheng Teng Hsu
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Publication number: 20060180817Abstract: An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.Type: ApplicationFiled: February 17, 2005Publication date: August 17, 2006Inventors: Sheng Hsu, Fengyan Zhang, Gregory Stecker, Robert Barrowcliff
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Publication number: 20060183305Abstract: A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a Si-rich Si oxide (SRSO) film on a substrate, doped with the first rare earth element; and, annealing the rare earth element-doped SRSO film. The first target is doped with a rare earth element such as erbium (Er), ytterbium (Yb), cerium (Ce), praseodymium (Pr), or terbium (Tb). The sputtering power is in the range of about 75 to 300 watts (W). Different sputtering powers are applied to the two targets. Also, deposition can be controlled by varying the effective areas of the two targets. For example, one of the targets can be partially covered.Type: ApplicationFiled: January 18, 2006Publication date: August 17, 2006Inventors: Wei Gao, Tingkai Li, Robert Barrowcliff, Yoshi Ono, Sheng Hsu
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Publication number: 20060160304Abstract: A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.Type: ApplicationFiled: January 19, 2005Publication date: July 20, 2006Inventors: Sheng Hsu, Fengyan Zhang, Gregory Stecker, Robert Barrowcliff
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Publication number: 20060124926Abstract: A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.Type: ApplicationFiled: January 26, 2006Publication date: June 15, 2006Inventors: Fengyan Zhang, Gregory Stecker, Robert Barrowcliff, Sheng Hsu
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Publication number: 20060099758Abstract: A method is provided for forming iridium oxide (IrOx) nanotubes. The method comprises: providing a substrate; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; introducing oxygen as a precursor reaction gas; establishing a final pressure in the range of 1 to 50 Torr; establishing a substrate, or chamber temperature in the range of 200 to 500 degrees C.; and using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx hollow nanotubes from the substrate surface. Typically, the (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor is initially heated in an ampule to a first temperature in the range of 60 to 90 degrees C., and the first temperature is maintained in the transport line introducing the precursor. The precursor may be mixed with an inert carrier gas such as Ar, or the oxygen precursor reaction gas may be used as the carrier.Type: ApplicationFiled: October 21, 2004Publication date: May 11, 2006Inventors: Fengyan Zhang, Robert Barrowcliff, Gregory Stecker, Sheng Hsu
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Publication number: 20060088993Abstract: A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.Type: ApplicationFiled: December 15, 2004Publication date: April 27, 2006Inventors: Fengyan Zhang, Gregory Stecker, Robert Barrowcliff, Sheng Hsu
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Publication number: 20060086314Abstract: Iridium oxide (IrOx) nanowires and a method forming the nanowires are provided. The method comprises: providing a growth promotion film with non-continuous surfaces, having a thickness in the range of 0.5 to 5 nanometers (nm), and made from a material such as Ti, Co, Ni, Au, Ta, polycrystalline silicon (poly-Si), SiGe, Pt, Ir, TiN, or TaN; establishing a substrate temperature in the range of 200 to 600 degrees C.; introducing oxygen as a precursor reaction gas; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx nanowires from the growth promotion film surfaces. The IrOx nanowires have a diameter in the range of 100 to 1000 ?, a length in the range of 1000 ? to 2 microns, an aspect ratio (length to width) of greater than 50:1. Further, the nanowires include single-crystal nanowire cores covered with an amorphous layer having a thickness of less than 10 ?.Type: ApplicationFiled: October 21, 2004Publication date: April 27, 2006Inventors: Fengyan Zhang, Robert Barrowcliff, Sheng Hsu
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Publication number: 20050014296Abstract: A method of forming an H2 passivation layer in an FeRAM includes preparing a silicon substrate; depositing a layer of TiOx thin film, where 0<x<2, on a damascene structure; plasma space etching of the Ti or TiOx thin film to form a TiOx sidewall; annealing the TiOx side wall thin film to form a TiO2 thin film; depositing a layer of ferroelectric material; and metallizing the structure to form a FeRAM.Type: ApplicationFiled: July 16, 2003Publication date: January 20, 2005Inventors: Tingkai Li, Wei Pan, Robert Barrowcliff, David Evans, Sheng Hsu
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Publication number: 20040203234Abstract: A method of forming a tungsten nitride thin film in an integrated circuit includes preparing a silicon substrate on a silicon wafer and placing the silicon wafer in a heatable chuck in a CVD vacuum chamber; placing a known quantity of a tungsten source in a variable-temperature bubbler to provide a gaseous tungsten source; setting the variable-temperature bubbler to a predetermined temperature; passing a carrier gas through the variable-temperature bubbler and carrying the gaseous tungsten source with the carrier gas into the CVD vacuum chamber; introducing a nitrogen-containing reactant gas into the CVD vacuum chamber; reacting the gaseous tungsten source and the nitrogen-containing reactant gas above the surface of the silicon wafer in a deposition process to deposit a WxNy thin film on the surface of the silicon wafer; and completing the integrated circuit containing the WxNy thin film.Type: ApplicationFiled: April 9, 2003Publication date: October 14, 2004Applicant: Sharp Laboratories of America, Inc.Inventors: Wei Pan, Robert Barrowcliff, David R Evans, Sheng Teng Hsu
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Patent number: 6090963Abstract: A metal(hfac), alkene ligand precursor has been provided. The alkene ligand includes double bonded carbon atoms, with first and second bonds to the first carbon atom, and third and fourth bonds to the second carbon atom. The first, second, third, and fourth bonds are selected from a the group consisting of H, C.sub.1 to C.sub.8 alkyl, C.sub.1 to C.sub.8 haloalkyl, and C.sub.1 to C.sub.8 alkoxyl. As a general class, these precursors are capable of high metal deposition rates and high volatility, despite being stable in the liquid phase at low temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described alkene ligand class of metal precursors.Type: GrantFiled: March 30, 1999Date of Patent: July 18, 2000Assignee: Sharp Laboratories of America, Inc.Inventors: Wei-Wei Zhuang, Tue Nguyen, Robert Barrowcliff, David Russell Evans, Sheng Teng Hsu