Abstract: A microinstruction address is determined in response to the content of an mediately preceding microinstruction. A data processing apparatus contains a memory for storing microinstructions at addressable locations. Testing bits are loaded into a test register while a microinstruction read from the memory is loaded into a microinstruction register.

Abstract: A plurality of sub-clock signals are derived from a main clock signal sou by advancing a shift register and a counter with pulses from the main clock source. The shift register is selectively loaded with a desired combination of sub-clock bits in response to a predetermined number of main clock pulses being supplied to the counter. The sub-clock signals are derived from output terminals at different stages of the shift register. The state of the sub-clock signals can be selectively frozen by decoupling pulses from the main clock source to inputs of the counter and shift register.