Patents by Inventor Robert Beat
Robert Beat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7302545Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.Type: GrantFiled: November 13, 2006Date of Patent: November 27, 2007Assignee: Broadcom CorporationInventor: Robert Beat
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Publication number: 20070055832Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.Type: ApplicationFiled: November 13, 2006Publication date: March 8, 2007Applicant: Broadom CorporationInventor: Robert Beat
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Patent number: 7136985Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.Type: GrantFiled: July 20, 2004Date of Patent: November 14, 2006Assignee: Broadcom CorporationInventor: Robert Beat
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Patent number: 7049851Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential, and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couplType: GrantFiled: February 28, 2005Date of Patent: May 23, 2006Assignee: Broadcom CorporationInventor: Robert Beat
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Publication number: 20050180240Abstract: An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.Type: ApplicationFiled: April 11, 2005Publication date: August 18, 2005Applicant: Broadcom CorporationInventor: Robert Beat
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Publication number: 20050141329Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential, and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couplType: ApplicationFiled: February 28, 2005Publication date: June 30, 2005Applicant: Broadcom CorporationInventor: Robert Beat
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Patent number: 6912173Abstract: An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.Type: GrantFiled: June 25, 2002Date of Patent: June 28, 2005Assignee: Broadcom CorporationInventor: Robert Beat
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Patent number: 6864721Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couplType: GrantFiled: August 29, 2002Date of Patent: March 8, 2005Assignee: Broadcom CorporationInventor: Robert Beat
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Publication number: 20040266027Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.Type: ApplicationFiled: July 20, 2004Publication date: December 30, 2004Applicant: Broadcom CorporationInventor: Robert Beat
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Patent number: 6789179Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.Type: GrantFiled: June 25, 2002Date of Patent: September 7, 2004Assignee: Broadcom CorporationInventor: Robert Beat
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Patent number: 6614701Abstract: Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each memory cell comprising: respective first and second transistors in cross-coupled arrangement to form a bistable latch, the drain of the first transistor representing a respective first node for storing a high or low potential state and being connected to a respective first semiconductor arrangement for replacing charge leaked from the first node and being connected to a respective first switching device, activatable by the common word-line, for coupling the respective first node to a respective first bit-line, the drain of the second transistor representing a respective second node for storing a high or low potential state and being connected to a respective second semiconductor arrangement for replacing charge leaked from the respective second node and being connected to a respective second switching device, activatable by the common word line, for couType: GrantFiled: April 10, 2002Date of Patent: September 2, 2003Assignee: STMicroelectronics LimitedInventors: William Bryan Barnes, Robert Beat
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Publication number: 20030006802Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couplType: ApplicationFiled: August 29, 2002Publication date: January 9, 2003Applicant: Broadcom UK Ltd.Inventor: Robert Beat
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Publication number: 20030007400Abstract: Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each memory cell comprising: respective first and second transistors in cross-coupled arrangement to form a bistable latch, the drain of the first transistor representing a respective first node for storing a high or low potential state and being connected to a respective first semiconductor arrangement for replacing charge leaked from the first node and being connected to a respective first switching means, activatable by the common word-line, for coupling the respective first node to a respective first bit-line, the drain of the second transistor representing a respective second node for storing a high or low potential state and being connected to a respective second semiconductor arrangement for replacing charge leaked from the respective second node and being connected to a respective second switching means, activatable by the common word line, for couplType: ApplicationFiled: April 10, 2002Publication date: January 9, 2003Inventors: William Bryan Barnes, Robert Beat
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Publication number: 20030005255Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.Type: ApplicationFiled: June 25, 2002Publication date: January 2, 2003Applicant: Broadcom CorporationInventor: Robert Beat
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Publication number: 20030002376Abstract: An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.Type: ApplicationFiled: June 25, 2002Publication date: January 2, 2003Applicant: Broadcom CorporationInventor: Robert Beat
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Patent number: 6456118Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential, and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couplType: GrantFiled: January 12, 2001Date of Patent: September 24, 2002Assignee: Broadcom CorporationInventor: Robert Beat
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Publication number: 20010022749Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couplType: ApplicationFiled: January 12, 2001Publication date: September 20, 2001Inventor: Robert Beat
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Patent number: 6052806Abstract: An integrated circuit device includes operational circuitry, for example, in the form of a memory for carrying out operations of the integrated circuit device. Additionally, at least one peripheral circuit is connected to the operational circuitry for carrying out at least one function in respect of the operational circuitry. Input means are provided to permit the input of command data in a normal mode of operation and to permit the input of test data in a test mode of operation. Control circuitry has an input to receive command data from the input means. The control circuitry is arranged to generate, in response to the command data, control signals to control at least one of the peripheral circuits in the normal mode of operation. A control bus is connected between the control circuitry and the peripheral circuits and is arranged to carry control signals from the control circuitry to at least one peripheral circuit.Type: GrantFiled: August 25, 1995Date of Patent: April 18, 2000Assignee: STMicroelectronics LimitedInventor: Robert Beat
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Patent number: 5959465Abstract: A method is provided for operating a programmable logic array in an integrated circuit. Each stage of the circuit is enabled only during the time necessary for that stage to propagate an incoming signal. Enable signals are generated for the stages of the circuit, using a dummy circuit which replicates elements of the circuit in dimension, orientation and connectivity. These elements provide a delay path, such that an input signal applied coincidentally to the programmable logic array circuit and the dummy circuit produces outputs of the dummy circuit which define times for applying and removing the enable signals from stages of the programmable logic array circuit.Type: GrantFiled: December 29, 1995Date of Patent: September 28, 1999Assignee: STMicroelectronics Ltd.Inventor: Robert Beat
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Patent number: 5687352Abstract: A memory device has a data storage portion and at least peripheral circuit connected to the data storage portion for carrying out a function with respect to the data storage portion. The memory device also has control circuitry connected to the at least one peripheral circuit and operable to provide a plurality of consecutive signals for controlling the function of said at least one peripheral circuit. The consecutive signals generated by the control circuitry are in the form of Gray code.Type: GrantFiled: August 25, 1995Date of Patent: November 11, 1997Assignee: SGS-Thomson Microelectronics LimitedInventor: Robert Beat