Abstract: This application discloses a system implementing tools and mechanisms to determine whether a portion of combinational logic in a first circuit design is equivalent to a portion of combinational logic in a second circuit design. When the portions of the combinational logic in the first circuit design and the second circuit design are not equivalent, the tools and mechanisms can sequentially expand the portions of the combinational logic in the first circuit design and the second circuit design, and determine whether the expanded portion of the combinational logic in the first circuit design is equivalent the expanded portion of the combinational logic in the second circuit design.

Abstract: This application discloses a system implementing tools and mechanisms to determine whether a portion of combinational logic in a first circuit design is equivalent to a portion of combinational logic in a second circuit design. When the portions of the combinational logic in the first circuit design and the second circuit design are not equivalent, the tools and mechanisms can sequentially expand the portions of the combinational logic in the first circuit design and the second circuit design, and determine whether the expanded portion of the combinational logic in the first circuit design is equivalent the expanded portion of the combinational logic in the second circuit design.

Abstract: This application discloses a system implementing tools and mechanisms to develop a vector stream for each input of a circuit design. Each vector stream can be configured to identify one or more operations in the circuit design having an output that depends on a corresponding input of the circuit design. The tools and mechanisms can select different vector streams to utilize for simulation of the circuit design based on value changes in a series of test vectors, and simulate the circuit design by performing operations identified by the selected vector streams with values from the corresponding test vectors. The tools and mechanisms can generate the series of test vectors with a pattern generator, which may be in a grey code sequence. The tools and mechanisms can determine whether the circuit design is equivalent to another circuit design by comparing the simulation results of the two circuit designs.

Abstract: A data surge protection module which can be added to data and control networks not having such protection. The use of quick connect/disconnect connectors allows the rapid installation or replacement of such modules. a built in ground plate and a braided low impedance conductor offer alternative grounding methods for the module. The module employs two or more diode steering bridges and uses a diode as the surge suppression element.

Abstract: A data surge protection module which can be added to data and control networks not having such protection. The use of quick connect/disconnect connectors allows the rapid installation or replacement of such modules. a built in ground plate and a braided low impedance conductor offer alternative grounding methods for the module. The module employs two or more diode steering bridges and uses a diode as the surge suppression element.

Abstract: A data surge protection module can be added to data and control networks not having such surge protection. The use of quick connect/disconnect connectors allows for the rapid installation and/or replacement of such modules. A built-in ground plate and a braided low impedance conductor offer alternative grounding for the module. The module employs two or more diode steering bridges and uses a diode as a surge suppression element.

Abstract: A data surge protection module can be added to data and control networks not having such surge protection. The use of quick connect/disconnect connectors allows for the rapid installation and/or replacement of such modules. A built-in ground plate and a braided low impedance conductor offer alternative grounding for the module. The module employs two or more diode steering bridges and uses a diode as a surge suppression element.

Abstract: A data surge protection module can be added to data and control networks not having such surge protection. The use of quick connect/disconnect connectors allows for the rapid installation and/or replacement of such modules. A built-in ground plate and a braided low impedance conductor offer alternative grounding for the module. The module employs two or more diode steering bridges and uses a diode as a surge suppression element.

Abstract: The present invention provides a method for generating a path delay fault test for sequential logic circuits along a desired signal path implementing a two rated speed clocking scheme. Although initialization is accomplished at a reduced clock speed, two functional clock cycles are required to fully activate the desired signal transition along the selected signal path lying between designated source and destination flip-flops. Importantly, prior to the second functional clock cycle that activates the signal transition, a first functional clock cycle attempted at the rated clock speed is used to initialize at least the source flip-flop. In so doing, the automatic test equipment (ATE) that applies the test vectors is allowed to ramp-up to the rated clock speed prior to having to critically apply at the rated speed the required test vectors so as to launch the desired signal transition.

Abstract: A test (i.e., a set of test vectors) for differentiating between two different integrated circuit versions (12,14) is established by first modeling the circuits in a simulated system such that: (a) the corresponding inputs of the circuits are coupled in parallel, (b) the corresponding outputs of the circuits are exclusively OR'd by a separate one of a plurality of exclusive OR gates (18.sub.1,18.sub.2,18.sub.3 . . . 18.sub.m), and (c) the outputs of the exclusive OR gates are OR'd by an OR gate (20). Thereafter, a set of test vectors is generated, using conventional techniques, such that the vectors, when input to the different-version integrated circuits, cause a predetermined logic level signal to the OR gate (20).