Abstract: An LBIST captures pseudo-random values from a pseudo-random pattern generator. Next, the LBIST stabilizes an untimed logic path by inputting the captured pseudo-random value into the untimed logic path. In turn, the LBIST tests one or more timed signal transitions that are dependent upon the stabilized untimed logic path.

Abstract: An LBIST captures pseudo-random values from a pseudo-random pattern generator. Next, the LBIST stabilizes an untimed logic path by inputting the captured pseudo-random value into the untimed logic path. In turn, the LBIST tests one or more timed signal transitions that are dependent upon the stabilized untimed logic path.

Abstract: The present invention is directed to an improved method, system and apparatus for self-testing an electronic device. A scan latch used in a multi-cycle bus is uniquely operated to generate signal transitions consistent with the normal operating speed of the device. This occurs even when a normal signal transition would not otherwise occur since the multi-cycle bus normally requires a plurality of clock pulses to create such signal transition. The logical states of master and slave clocks associated with test scan logic are used to automatically cause the output of a scan latch to invert its output or switch from its previous state at each rising edge of the slave clock that is not preceded by a master or scan clock.

Abstract: An apparatus and method for optimum transparent latch placement in a macro design are provided. With the apparatus and method, a tree graph data structure is generated to represent the design wherein nodes of the tree graph data structure represent macros of the design. Each node of the tree graph data structure is augmented to include a maximum latch number and a clocking domain. Any leaf nodes of the tree graph data structure that cannot have latches placed in them, but have latch placement requirements, have their latch placement requirements added to their parent node if their parent node has more than one child node. The tree graph data structure is traversed to find the most timing critical nodes with timing requirements that have not been satisfied. A most timing critical path of these paths is identified. Intermediate nodes along this path are examined to determine if there are any latch placement requirements that must be met for the nodes.

Abstract: An apparatus and method for optimum transparent latch placement in a macro design are provided. With the apparatus and method, a tree graph data structure is generated to represent the design wherein nodes of the tree graph data structure represent macros of the design. Each node of the tree graph data structure is augmented to include a maximum latch number and a clocking domain. Any leaf nodes of the tree graph data structure that cannot have latches placed in them, but have latch placement requirements, have their latch placement requirements added to their parent node if their parent node has more than one child node. The tree graph data structure is traversed to find the most timing critical nodes with timing requirements that have not been satisfied. A most timing critical path of these paths is identified. Intermediate nodes along this path are examined to determine if there are any latch placement requirements that must be met for the nodes.