Abstract: Yield excursions in the manufacturing process today require an expensive, long and tedious physical failure analysis process to identify the root cause. Techniques are disclosed herein for efficiently identifying the root-cause of a manufacturing yield excursion by analyzing fail data collected from the production test environment. In particular, statistical hypothesis testing is used in a novel way to analyze logic diagnosis data along with information on physical features in the design layout and reliably identify the cause of the yield excursion.

Abstract: A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.

Abstract: A method and computer program for detecting and locating defects in integrated circuit die from stimulation of statistical outlier signatures includes receiving as input a test value of an electrical parameter measured for each of a plurality of identically designed electrical circuits, identifying one of the identically designed electrical circuits as an outlier for which the test value of the electrical parameter varies from a mean test value of the electrical parameter for the plurality of identically designed electrical circuits by at least a selected difference, monitoring the test value while subjecting a location on the outlier to a stimulus to detect a change in the test value as a function of the location, and generating as output the location for which the change in the test value is detected to identify a defect in the outlier.

Abstract: A method for a modified binary search includes steps of: selecting a parameter having a distribution of values, selecting a probability density function representative of the distribution of values of the selected parameter, defining a substantially equal probability weighted binary test interval from the probability density function for each of a selected number of test intervals over a selected test range, translating the weighted binary test intervals to obtain a highest resolution at a target point of the selected parameter, and skewing the translated and weighted binary test intervals by a selected scaling function to generate a modified binary test interval for each of the selected number of test intervals over the selected test range.

Abstract: A method and computer program for screening defects in integrated circuit die includes steps of: (a) receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die; (b) generating a test matrix from the quiescent current measurements for each die in the sample lot; (c) computing a de-mixing matrix from independent component analysis that models passing die in the sample lot; (d) generating a matrix of sources as a product of the test matrix and the de-mixing matrix; (e) normalizing the matrix of sources to zero mean and unit variance; (f) selecting a statistical limit of the passing die in the sample lot to determine a maximum and a minimum quiescent current limit for each of the sources; and (g) generating as output the maximum and the minimum quiescent current limit for each of the sources.

Abstract: A self-timed scan circuit includes a multiplexer for selecting either a data input or a test input in response to an internal test enable signal and for generating a multiplexed output; a latch coupled to the multiplexer for generating a latched output in response to a next clock pulse; and a timing control circuit for generating the internal test enable signal in response to a global test enable signal wherein the internal test enable signal is set to logic one when the global test enable signal is set to logic one and wherein the internal test enable signal is set to logic zero in response to the next clock pulse.

Abstract: A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF fault, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.

Abstract: A method of screening defects includes steps of: (a) measuring a quiescent current at a first supply voltage for each of a plurality of devices; (b) measuring a quiescent current at a second supply voltage for each of the plurality of devices; (c) generating a plot of the quiescent current measured at the first supply voltage vs. the quiescent current measured at the second supply voltage for each of the plurality of devices; (d) determining a range of intrinsic variation of quiescent current in the plot; and (e) identifying any of the plurality of devices corresponding to a measurement plotted outside the range of intrinsic variation as defective.

Abstract: A self-timed scan circuit includes a multiplexer for selecting either a data input or a test input in response to an internal test enable signal and for generating a multiplexed output; a latch coupled to the multiplexer for generating a latched output in response to a next clock pulse; and a timing control circuit for generating the internal test enable signal in response to a global test enable signal wherein the internal test enable signal is set to logic one when the global test enable signal is set to logic one and wherein the internal test enable signal is set to logic zero in response to the next clock pulse.

Abstract: A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-at fault patterns to achieve maximum stuck-at fault and transition delay fault coverage; (c) truncating the estimated number of transition delay fault patterns to generate a truncated set of transition delay fault patterns so that the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns achieve maximum stuck-at fault and transition delay fault coverage within a selected scan memory limit; and (d) generating as output the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns.

Abstract: A method of screening defects includes steps of: (a) measuring a quiescent current at a first supply voltage for each of a plurality of devices; (b) measuring a quiescent current at a second supply voltage for each of the plurality of devices; (c) generating a plot of the quiescent current measured at the first supply voltage vs. the quiescent current measured at the second supply voltage for each of the plurality of devices; (d) determining a range of intrinsic variation of quiescent current in the plot; and (e) identifying any of the plurality of devices corresponding to a measurement plotted outside the range of intrinsic variation as defective.

Abstract: A method for a modified binary search includes steps of: selecting a parameter having a distribution of values, selecting a probability density function representative of the distribution of values of the selected parameter, defining a substantially equal probability weighted binary test interval from the probability density function for each of a selected number of test intervals over a selected test range, translating the weighted binary test intervals to obtain a highest resolution at a target point of the selected parameter, and skewing the translated and weighted binary test intervals by a selected scaling function to generate a modified binary test interval for each of the selected number of test intervals over the selected test range.