Patents by Inventor Robert Bertram
Robert Bertram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9744683Abstract: A machine for forming insulating panels from pieces includes a moving device with pieces thereon, where every other piece is upside down from a position that is desired and a flipping zone comprising a flipping machine. The flipping machine rotates the upside down pieces 180 degrees and releases the now right side up pieces for further processing.Type: GrantFiled: February 27, 2014Date of Patent: August 29, 2017Assignee: IDEAL PRODUCTS OF CANADAInventor: Robert Bertram
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Publication number: 20150239142Abstract: A machine for forming insulating panels from pieces includes a moving device with pieces thereon, where every other piece is upside down from a position that is desired and a flipping zone comprising a flipping machine. The flipping machine rotates the upside down pieces 180 degrees and releases the now right side up pieces for further processing.Type: ApplicationFiled: February 27, 2014Publication date: August 27, 2015Applicant: Ideal Products of CanadaInventor: Robert Bertram
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Patent number: 8803216Abstract: A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.Type: GrantFiled: March 20, 2006Date of Patent: August 12, 2014Assignees: Spansion, LLC, Advanced Micro Devices, Inc.Inventors: Meng Ding, Lei Xue, Mark Randolph, Chi Chang, Robert Bertram Ogle, Jr.
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Patent number: 8563441Abstract: Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures for rounding the corners and edges between the top surfaces and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures are annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.Type: GrantFiled: April 28, 2008Date of Patent: October 22, 2013Assignee: Spansion LLCInventors: Yi Ma, Robert Bertram Ogle
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Patent number: 8357457Abstract: A wood composite including a reinforced laminate for overcoming interlaminate shear failure includes the use of an adhesive to form a strong mechanical bond between the adhesive and the wood and a strong chemical bond between the adhesive and the reinforced laminate. The reinforcement is a fiber reinforced polymer (FRP) composite comprising a thermoset polyurethane resin matrix. An emulsion polymer isocyanate (EPI) adhesive is used to bond the FRP composite to wood.Type: GrantFiled: August 10, 2009Date of Patent: January 22, 2013Inventors: David E. Green, Robert Bertram
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Publication number: 20120197729Abstract: A system and method for implementing promotions in a retail environment is provided. Transceivers located at one or more locations within the retail environment are adapted for communication with personal mobile devices carried by shoppers. Promotions can be offered and accepted based on factors such as a shopper's location within a store, shopper identity, shopper purchase history, shopper promotion redemption history, date and time and other factors. Applicable promotions are then activated within the retailer point-of-sale system for application during checkout.Type: ApplicationFiled: January 30, 2012Publication date: August 2, 2012Applicant: UNICOUS MARKETING, INC.Inventors: Robert Bertram, Shakh Alam
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Patent number: 7863175Abstract: A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in a same processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.Type: GrantFiled: December 21, 2006Date of Patent: January 4, 2011Assignees: Spansion LLC, Globalfoundries Inc.Inventors: Robert Bertram Ogle, Joong Jeon, Eric Paton, Austin Frenkel
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Publication number: 20100035015Abstract: A wood composite including a reinforced laminate for overcoming interlaminate shear failure includes the use of an adhesive to form a strong mechanical bond between the adhesive and the wood and a strong chemical bond between the adhesive and the reinforced laminate. The reinforcement is a fiber reinforced polymer (FRP) composite comprising a thermoset polyurethane resin matrix. An emulsion polymer isocyanate (EPI) adhesive is used to bond the FRP composite to wood.Type: ApplicationFiled: August 10, 2009Publication date: February 11, 2010Inventors: David E. Green, Robert Bertram
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Publication number: 20090269918Abstract: Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures for rounding the corners and edges between the top surfaces and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures are annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.Type: ApplicationFiled: April 28, 2008Publication date: October 29, 2009Inventors: Yi Ma, Robert Bertram Ogle
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Publication number: 20080150028Abstract: A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a semiconductor device. An exemplary method can include removing an oxide from a surface of a first poly layer and forming a second poly layer on the first poly layer in a processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Robert Bertram Ogle, Joong Jeon, Jon Kluth
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Publication number: 20080149986Abstract: A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in a same processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Robert Bertram Ogle, Jr., Joong Jeon, Austin Frenkel, Eric Paton
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Publication number: 20080079061Abstract: According to one exemplary embodiment, a structure, for example a flash memory cell, comprises a transistor gate dielectric stack situated on a semiconductor substrate. The transistor gate dielectric stack includes a bottom oxide layer, a silicon-rich nitride layer situated on the bottom oxide layer, a low silicon-rich nitride layer situated on the silicon-rich nitride layer, and a top oxide layer situated on the low silicon-rich nitride layer. This embodiment results in a nitride based flash memory cell having improved program speed and retention while maintaining a high erase speed. In another embodiment, a flash memory cell may further comprise a high-K dielectric layer situated on the transistor gate dielectric stack.Type: ApplicationFiled: September 28, 2006Publication date: April 3, 2008Inventors: Meng Ding, Amol Joshi, Takashi Orimoto, Jayendra Bhakta, Lei Xue, Satoshi Torii, Robert Bertram Ogle
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Patent number: 6709927Abstract: A process to deposit a silicon dioxide layer on a silicon nitride layer for an ONO stack of a floating gate transistor. Silicon dioxide is deposited on a silicon nitride layer and annealed in a batch furnace or a single wafer rapid thermal anneal tool in a nitrogen oxide (NO) or nitrous oxide (N2O) ambient environment.Type: GrantFiled: August 10, 2001Date of Patent: March 23, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Robert Bertram Ogle, Jr., Arvind Halliyal
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Patent number: 6451641Abstract: A process for fabricating a semiconductor device, including providing a semiconductor substrate; depositing on the semiconductor substrate a layer of a high-K gate dielectric material; depositing on the gate dielectric material layer a polysilicon or polysilicon-germanium gate electrode layer, in which the step of depositing the polysilicon or polysilicon-germanium gate electrode layer includes providing non-reducing conditions in a CVD apparatus.Type: GrantFiled: February 27, 2002Date of Patent: September 17, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Arvind Halliyal, Robert Bertram Ogle, Jr., Joong S. Jeon, Fred Cheung, Effiong Ibok
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Patent number: 6245689Abstract: A process for growing an ultra-thin dielelctric layer for use as a MOSFET gate or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density electron traps, and impedes dopant impurity diffusion from/to the dielelctric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.Type: GrantFiled: September 8, 1998Date of Patent: June 12, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Ming-Yin Hao, Robert Bertram Ogle, Jr., Derick Wristers
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Patent number: 5939763Abstract: A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.Type: GrantFiled: September 5, 1996Date of Patent: August 17, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Ming-Yin Hao, Robert Bertram Ogle, Jr., Derick Wristers
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Patent number: D646363Type: GrantFiled: December 15, 2010Date of Patent: October 4, 2011Inventor: Robert Bertram
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Patent number: D647183Type: GrantFiled: December 15, 2010Date of Patent: October 18, 2011Inventor: Robert Bertram