Abstract: A novel and useful digitally controlled injection-locked RF oscillator with an auxiliary loop. The oscillator is injection locked to a time delayed version of its own resonating voltage (or its second harmonic) and its frequency is modulated by manipulating the phase and amplitude of injected current. The oscillator achieves a narrow modulation tuning range and fine step size of an LC tank based digitally controlled oscillator (DCO). The DCO first gets tuned to its center frequency by means of a conventional switched capacitor array. Frequency modulation is then achieved via a novel method of digitally controlling the phase and amplitude of injected current into the LC tank generated from its own resonating voltage. A very linear deviation from the center frequency is achieved with a much lower gain resulting in a very fine resolution DCO step size and high linearity without needing to resort to oversampled noise shaped dithering.

Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.

Abstract: The invention provides a transmitter comprising two (or more) phase locked loops controlling respective oscillators, and implementing different phase modulation. Multiple phases are derived from the respective oscillators, and an edge rotator forms an output signal from a combination of the phases. The oscillators can operate at different frequencies, neither of which is an integer multiple of the other, whereas the output signals of the multiplexers of the first and second phase locked loops are closer in frequency and can be the same. This reduces the problem of pulling, with a circuit that can be implemented with low power and area and with the versatility of being digitally intensive.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.

Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.

Abstract: A phase-locked loop (PLL) is provided. The PLL comprises a clock adjuster configured to receive an initial clock signal having an initial frequency and a mode control signal. The clock adjuster is configured to modify the initial clock signal into a modified clock signal based on the mode control signal. The PLL is configured such that a loop bandwidth is equal to a specified bandwidth. When the modified clock signal is changed, a loop gain of a loop filter is adjusted such that the loop bandwidth is substantially equal to the specified bandwidth. When the modified clock signal is changed, an oscillator tuning word (OTW) signal is modified into a normalized OTW signal such that the loop bandwidth is substantially equal to the specified bandwidth.

Abstract: A phase-locked loop (PLL) is provided. The PLL comprises a dithering circuit that is configured to receive a second tuning signal, and dither the second tuning signal to generate a dither signal to decrease a magnitude of a spur of the PLL. The dither signal is used by a digitally controlled oscillator (DCO) to generate an output signal of the PLL. Operation of the dithering circuit is controlled using a spur-cancel control circuit. The spur-cancel control circuit receives a frequency command word (FCW) signal and determines a value of an enable signal based on the FCW signal. In some embodiments, the dithering circuit dithers the second tuning signal based on the enable signal.

Abstract: A quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a 360 degree phase shift around a loop. The oscillation frequency of the oscillator is the same as the resonant frequency of each LC tank, therefore it avoids quality factor degradation of LC tanks found in the prior art. In one example embodiment, class-D amplifiers are used to drive each of the LC tanks Capacitor banks before at the input and output of the buffers provide coarse and fine tuning of the frequency of oscillation. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on.

Abstract: A method of estimating gain of a time-to-digital converter (TDC) includes: capturing a TDC output sample; calculating a gradient in response to the TDC output sample; and adjusting a TDC normalizing gain based on the calculating step. Another method of calibrating gain of a TDC includes: capturing a phase error which is derived from a TDC output sample, a reference phase and a variable phase; calculating a gradient in response to the phase error; and adjusting a TDC normalizing gain based on the calculating step.

Abstract: A novel and useful oscillator topology demonstrating an improved phase noise performance that exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The oscillator is based on enforcing a pseudo-square voltage waveform around an LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. Alternatively, the oscillator is based on enforcing clipped oscillation waveform by increasing the second harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator's effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved.

Abstract: A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a period extender, a phase finder and a time-to-digital converter. The period extender is configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator. The phase finder is configured for sampling the oscillator output signal with the M*N-phased oscillator output signals to calculate an estimated value of the fractional phase part. The time-to-digital converter is configured to calculate a precise value of the fractional phase part within one sub-period.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: A novel and useful high-order discrete-time charge rotating (CR) infinite impulse response (IIR) low-pass filter is presented. The filter utilizes capacitors and a gm-cell, rather than operational amplifiers, and is thus compatible with digital nanoscale technology. A 7th-order charge-sampling and 6th-order voltage-sampling discrete time filter is disclosed. The order of the filter is easily extendable to higher orders. The charge rotating filter is process-scalable with Moore's law and amenable to digital nanoscale CMOS technology. Bandwidth of this filter is precise and robust to PVT variation. The filter exhibits very low power consumption per filter pole, low input-referred noise, wide tuning range, excellent linearity and low area per minimum bandwidth and filter pole.

Abstract: A novel and useful millimeter-wave digitally controlled oscillator (DCO) that achieve a tuning range greater than 10% and fine frequency resolution less than 1 MHz. Switched metal capacitors are distributed across a passive resonator for tuning the oscillation frequency. To obtain sub-MHz frequency resolution, tuning step attenuation techniques are used that exploit an inductor and a transformer. A 60-GHz fine-resolution inductor-based DCO (L-DCO) and a 60 GHz transformer-coupled DCO (T-DCO), both fabricated in 90 nm CMOS, are disclosed. The phase noise of both DCOs is lower than ?90.5 dBc/Hz at 1 MHz offset across 56 to 62 GHz frequency range. The T-DCO achieves a fine frequency tuning step of 2.5 MHz, whereas the L-DCO tuning step is over one order of magnitude finer at 160 kHz.

Abstract: A digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.

Abstract: A discrete-time filter for filtering an input signal comprises a switched capacitor network, the switched capacitor network comprising an input and an output, a number of switched capacitor paths arranged in parallel between the input and the output, each switched capacitor path comprising a capacitor, and a switch circuitry for switching each capacitor at a different time instant for outputting a filtered input signal.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.