Patents by Inventor Robert Brady Benware
Robert Brady Benware has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10496779Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.Type: GrantFiled: September 12, 2016Date of Patent: December 3, 2019Assignee: Mentor Graphics CorporationInventors: Robert Brady Benware, Wu-Tung Cheng, Christopher Schuermyer, Jonathan J. Muirhead, Chen-Yi Chang
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Patent number: 10234502Abstract: Various aspects of the disclosed technology relate to circuit defect diagnosis based on sink cell fault models. Defect candidates are determined based on path-tracing from failing bits into the circuit design. Based on the defect candidates and one or more conventional fault models, failing test pattern simulations are performed to determine initial defect suspects. Initial defective sink cell suspects are then determined by comparing driving strengths for fan-out cells of the initial defect suspects with driving strengths for corresponding driver cells. Defective sink cell suspects may be identified in the initial defective sink cell suspects based on fault effect propagations and passing test pattern simulations.Type: GrantFiled: March 9, 2017Date of Patent: March 19, 2019Assignee: Mentor Graphics CorporationInventors: Huaxing Tang, Manish Sharma, Robert Brady Benware, Wu-Tung Cheng
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Publication number: 20170103158Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.Type: ApplicationFiled: September 12, 2016Publication date: April 13, 2017Applicant: Mentor Graphics CorporationInventors: Robert Brady Benware, Wu-Tung Cheng, Christopher Schuermyer, Jonathan J. Muirhead, Chen-Yi Chang
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Patent number: 9443051Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.Type: GrantFiled: August 22, 2013Date of Patent: September 13, 2016Assignee: Mentor Graphics CorporationInventors: Robert Brady Benware, Wu-Tung Cheng, Christopher Schuermyer, Jonathan J Muirhead, Chen-Yi Chang
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Patent number: 9378327Abstract: Aspects of the disclosed technology relate to techniques for determining canonical forms of layout patterns. Coordinates of vertices of geometric elements in a window of a layout design are first transformed into new coordinates of the vertices, wherein the coordinates of vertices do not comprise clipped coordinates and the transforming comprises: performing a translation on the coordinates of vertices based on differences between maximum and minimum X/Y coordinate values of the vertices. Based on sums of X/Y coordinate values of the new coordinates of the vertices, a canonical form of the geometric elements is determined. The canonical form coordinates of the vertices may then be determined and sorted. The sorted canonical form coordinates may be employed for pattern matching.Type: GrantFiled: November 10, 2014Date of Patent: June 28, 2016Assignee: Mentor Graphics CorporationInventors: Wu-Tung Cheng, Manish Sharma, Robert Brady Benware, Robert Randal Klingenberg
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Patent number: 9336107Abstract: Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.Type: GrantFiled: November 19, 2012Date of Patent: May 10, 2016Assignee: Mentor Graphics CorporationInventors: Huaxing Tang, Yu Huang, Wu-Tung Cheng, Robert Brady Benware, Xiaoxin Fan
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Patent number: 9244125Abstract: Aspects of the invention relate to techniques for chain fault diagnosis based on dynamic circuit design partitioning. Fan-out cones for scan cells of one or more faulty scan chains of a circuit design are determined and combined to derive a forward-tracing cone. Fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design are determined and combined to derive a backward-tracing cone. By determining intersection of the forward-tracing cone and the backward-tracing cone, a chain diagnosis sub-circuit for the test failure file is generated. Using the process, a plurality of chain diagnosis sub-circuits may be generated for a plurality of test failure files. Scan chain fault diagnosis may then be performed on the plurality of chain diagnosis sub-circuits with a plurality of computers.Type: GrantFiled: October 25, 2013Date of Patent: January 26, 2016Assignee: Mentor Graphics CorporationInventors: Yu Huang, Huaxing Tang, Wu-Tung Cheng, Robert Brady Benware, Manish Sharma, Xiaoxin Fan
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Publication number: 20150234978Abstract: Various aspects of the disclosed technology relate to cell internal defect diagnosis techniques. Defect candidates are first determined based on path-tracing through a circuit design. Then, cell internal defect suspects are determined from the defect candidates based on simulating failing test patterns by using cell internal fault models. The defect candidate determination may be further based on simulating the failing test patterns by using conventional fault models. The cell internal defect suspect determination may be further based on simulating passing test patterns by using the cell internal fault models.Type: ApplicationFiled: February 13, 2015Publication date: August 20, 2015Inventors: Huaxing Tang, Robert Brady Benware, Friedrich Hapke, Wu-Tung Cheng, Manish Sharma
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Publication number: 20150135151Abstract: Aspects of the disclosed technology relate to techniques for determining canonical forms of layout patterns. Coordinates of vertices of geometric elements in a window of a layout design are first transformed into new coordinates of the vertices, wherein the coordinates of vertices do not comprise clipped coordinates and the transforming comprises: performing a translation on the coordinates of vertices based on differences between maximum and minimum X/Y coordinate values of the vertices. Based on sums of X/Y coordinate values of the new coordinates of the vertices, a canonical form of the geometric elements is determined. The canonical form coordinates of the vertices may then be determined and sorted. The sorted canonical form coordinates may be employed for pattern matching.Type: ApplicationFiled: November 10, 2014Publication date: May 14, 2015Inventors: Wu-Tung Cheng, Manish Sharma, Robert Brady Benware, Robert Randal Klingenberg
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Patent number: 9026874Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.Type: GrantFiled: December 9, 2013Date of Patent: May 5, 2015Assignee: Mentor Graphics CorporationInventors: Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Robert Brady Benware, Mark A. Kassab
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Patent number: 8930782Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a layout-aware diagnosis method. Based on the suspect information, potential root causes for the plurality of failing dies, and suspect feature weights and total feature weights for each of the potential root causes may then be determined. Next, the probability information of observing a particular suspect that is related to a particular root cause may be extracted. Finally, an expectation-maximization analysis may be conducted for generating the root cause distribution information based on the probability information and the suspect information. Heuristic information may be used to prevent the analysis from over-fitting.Type: GrantFiled: May 16, 2012Date of Patent: January 6, 2015Assignee: Mentor Graphics CorporationInventor: Robert Brady Benware
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Publication number: 20140164859Abstract: Aspects of the invention relate to techniques for chain fault diagnosis based on dynamic circuit design partitioning. Fan-out cones for scan cells of one or more faulty scan chains of a circuit design are determined and combined to derive a forward-tracing cone. Fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design are determined and combined to derive a backward-tracing cone. By determining intersection of the forward-tracing cone and the backward-tracing cone, a chain diagnosis sub-circuit for the test failure file is generated. Using the process, a plurality of chain diagnosis sub-circuits may be generated for a plurality of test failure files. Scan chain fault diagnosis may then be performed on the plurality of chain diagnosis sub-circuits with a plurality of computers.Type: ApplicationFiled: October 25, 2013Publication date: June 12, 2014Applicant: Mentor Graphics CorporationInventors: Yu Huang, Huaxing Tang, Wu-Tung Cheng, Robert Brady Benware, Manish Sharma, Xiaoxin Fan
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Patent number: 8707232Abstract: Aspects of the invention relate to techniques for fault diagnosis based on circuit design partitioning. According to various implementations of the invention, a circuit design of a failing die is first partitioned into a plurality of sub-circuits. The sub-circuits may be formed based on fan-in cones of observation points. Shared gate ratios may be used as a metric for adding fan-in cones of observation points into a sub-circuit. Based on test patterns and the sub-circuits, sub-circuit test patterns are determined. Fault diagnosis is then performed on the sub-circuits. The sub-circuit fault diagnosis comprises extracting sub-circuit failure information from the failure information for the failing die. The sub-circuit fault diagnosis may employ fault-free values for boundary gates in the sub-circuits.Type: GrantFiled: June 8, 2012Date of Patent: April 22, 2014Assignee: Mentor Graphics CorporationInventors: Huaxing Tang, Wu-Tung J. Cheng, Robert Brady Benware, Xiaoxin Fan
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Publication number: 20140101506Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.Type: ApplicationFiled: December 9, 2013Publication date: April 10, 2014Applicant: MENTOR GRAPHICS CORPORATIONInventors: Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Robert Brady Benware, Mark A. Kassab
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Publication number: 20140059511Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.Type: ApplicationFiled: August 22, 2013Publication date: February 27, 2014Applicant: Mentor Graphics CorporationInventors: Robert Brady Benware, Wu-Tung Cheng, Christopher Schuermyer, Jonathan J. Muirhead, Leo Chang
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Patent number: 8607107Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.Type: GrantFiled: April 20, 2011Date of Patent: December 10, 2013Assignee: Mentor Graphics CorporationInventors: Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Robert Brady Benware, Mark A Kassab
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Publication number: 20130024830Abstract: Aspects of the invention relate to techniques for fault diagnosis based on circuit design partitioning. According to various implementations of the invention, a circuit design of a failing die is first partitioned into a plurality of sub-circuits. The sub-circuits may be formed based on fan-in cones of observation points. Shared gate ratios may be used as a metric for adding fan-in cones of observation points into a sub-circuit. Based on test patterns and the sub-circuits, sub-circuit test patterns are determined. Fault diagnosis is then performed on the sub-circuits. The sub-circuit fault diagnosis comprises extracting sub-circuit failure information from the failure information for the failing die. The sub-circuit fault diagnosis may employ fault-free values for boundary gates in the sub-circuits.Type: ApplicationFiled: June 8, 2012Publication date: January 24, 2013Inventors: Huaxing Tang, Wu-Tung J Cheng, Robert Brady Benware, Xiaoxin Fan
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Publication number: 20120297264Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a layout-aware diagnosis method. Based on the suspect information, potential root causes for the plurality of failing dies, and suspect feature weights and total feature weights for each of the potential root causes may then be determined. Next, the probability information of observing a particular suspect that is related to a particular root cause may be extracted. Finally, an expectation-maximization analysis may be conducted for generating the root cause distribution information based on the probability information and the suspect information. Heuristic information may be used to prevent the analysis from over-fitting.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Inventor: Robert Brady Benware
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Publication number: 20110258504Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.Type: ApplicationFiled: April 20, 2011Publication date: October 20, 2011Inventors: Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Robert Brady Benware, Mark A. Kassab