Abstract: Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Abstract: A system, method and interface for compiling literary works from specialized databases and/or from unique interfaces is provided, including a custom database compiled from plural existing literary indexes, wherein a master index is harmonized from said existing indexes according to common terms (e.g., book, chapter and verse for biblical indexes) with deleted duplicates. In exemplary embodiments, the master index is also augmented by ingestion of additional literary works in digital form that are chopped up based on said common terms (e.g., book, chapter, verse) extracted from the literary work.

Abstract: Methods and apparatus for mapping memory allocation to DRAM dies of a stacked memory modules are described herein. Memory address ranges in a module employing 3DS (three dimensional stacked) DRAMs (Dynamic Random Access Memories) comprising stacked DRAM dies are mapped to DRAM dies in the module based on a layer of the DRAM dies, where dies in different layers have different thermal dissipation characteristic. Chunks of the memory address range are allocated to software entities such as virtual machines (VMs) and/or applications based on a memory access rate of the VMs/applications and the thermal dissipation characteristics of the DRAM die layers, wherein VMs/applications with higher memory access rate are allocated memory on DRAM dies with higher thermal dissipation. In one aspect, memory ranks are associated with respective die layers. In response to detection of change in access rates, memory may be migrated between ranks. Interleaving at multiple levels is also supported.

Abstract: An apparatus comprising a first memory interface of a first type to couple to at least one first memory device; a second memory interface of a second type to couple to at least one second memory device; and circuitry to interleave memory requests targeting contiguous memory addresses among the at least one first memory device and the at least one second memory device.

Abstract: Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

Abstract: Systems, apparatuses and methods may provide for technology that detects a misalignment condition, wherein the misalignment condition includes a memory map being misaligned with a granularity of a register, automatically appends a protected range to the memory map, wherein the protected range eliminates the misalignment condition, and defines an operational characteristic of the memory map via the register. In one example, the protected range is a non-existent memory (NXM) range appended via a source address decoder (SAD) rule, the register is a memory type range register (MTRR), and the operational characteristic is a cache characteristic.

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Abstract: A system, method and interface for compiling literary works from specialized databases and/or from unique interfaces is provided, including a custom database compiled from plural existing literary indexes, wherein a master index is harmonized from said existing indexes according to common terms (e.g., book, chapter and verse for biblical indexes) with deleted duplicates. In exemplary embodiments, the master index is also augmented by ingestion of additional literary works in digital form that are chopped up based on said common terms (e.g., book, chapter, verse) extracted from the literary work.

Abstract: A method and a device are disclosed including a clothing article with an embedded Data Measurement and Processing Module configured to measure a dynamic characteristic of a predefined significant impact to the user of the clothing article, and further including a video capturing device which provides video scenes related to the impact. In various embodiments, the embedded data collection and measurement module includes a multi-axis accelerometer and a processor, such as a microcontroller, coupled with the accelerometer to calculate a magnitude and direction of the imparted force, and a video camera that is configured to relate its different captured scenes to predefined significant impacts within each scene. In other various embodiments, the processor and/or the video capturing device may communicate collected and/or calculated data to a storage device and/or an external host computer for future analysis and use.

Abstract: Apparatus and methods are disclosed including client and/or server computing devices, such as smartphones, laptop computers, servers, and the like, having application software thereon configured to award credit points towards the purchase of goods and services from third parties upon meeting predefined milestones associated with the taking of online tests, educational courses or modules.

Abstract: The present disclosure relates to attempting to maintain and/or repair the embedded software components of a computer and, more specifically, to attempting to maintain and/or repair the embedded software components of a server utilizing a service processor.

Abstract: Disclosed is a catheter guide for female self-catheterization to assist in guiding a catheter into the user's urethra. The catheter guide includes a hand-held guide with a vaginal insert portion joined to a handle at a fixed or an adjustable angle. There is an enclosed or open canal in the vaginal insert portion which can be aligned with the urethra, when the insert portion is in the vagina, and through which a catheter can be guided into the urinary tract.

Abstract: System(s) and method(s) for analysis and design of genome sequences are provided. A graph representation of a genome sequence facilitates generation of a thermodynamic based quantity, e.g., an entropy-based and enthalpy-based thermodynamic tolerance [?], which in turn affords estimation of a gene sequence potential function that depends at least upon structural and functional properties of the gene sequence. The gene sequence potential (?) is determined, at least in part, via a generalized Schrödinger equation for the thermodynamic tolerance. Gene sequence potential and thermodynamic tolerance [?], and derived quantities, like thermodynamic tolerance profile and generalized homology, provide an analytic instrument for characterization of natural and synthetic gene sequences, and in conjunction with graph-based algorithms embodies a tool for design of genome sequences with predetermined properties.

Abstract: Disclosed is a catheter guide for female self-catheterization to assist in guiding a catheter into the user's urethra. The catheter guide includes a hand-held guide with a vaginal insert portion joined to a handle at a fixed or an adjustable angle. There is an enclosed or open canal in the vaginal insert portion which can be aligned with the urethra, when the insert portion is in the vagina, and through which a catheter can be guided into the urinary tract.

Abstract: The present disclosure relates to attempting to maintain and/or repair the embedded software components of a computer and, more specifically, to attempting to maintain and/or repair the embedded software components of a server utilizing a service processor.