Patents by Inventor Robert Brian Likovich

Robert Brian Likovich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7917908
    Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich, Jr., Wesley Erich Queen, Michael Steven Siegel
  • Patent number: 7454753
    Abstract: A generic method and apparatus for managing semaphores in a multi-threaded processing system has a storage area for each of the threads in the processing system. Each storage area includes a first part for storing at least one indicia for identifying at least one unique semaphore from a plurality of semaphores utilized by the multi-threaded processing system and a second part for storing an indicia for indicating a locked status for the stored semaphore. A thread requiring a semaphore sends a semaphore lock request to the semaphore manager which examines the contents of all of the storage areas to determine the status of the requested semaphore. If the requested semaphore is not locked, it is locked for the requesting thread by inserting the requested semaphore and locked status in the memory location assigned to the requesting thread.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Gordon Taylor Davis, Marco Heddes, Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich, Jr.
  • Publication number: 20080244130
    Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 2, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich, Wesley Erich Queen, Michael Steven Siegel
  • Patent number: 7406690
    Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: July 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich, Jr., Wesley Erich Queen, Michael Steven Siegel
  • Patent number: 7246332
    Abstract: Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments include constraining one or more fields of a record and determining delay amounts based on the resulting parameters, where the final delay amount includes a delay buffer and a net of delay amounts associated with the parameters. Embodiments may also include determining a value of a next bit to be sent to the I/O bus and, after waiting the delay amount, driving the bit on the bus to the next bit value. Parameters may include skew, jitter, duty cycle distortion, voltage reference distortion, and drift of any of these parameters. Further embodiments may include signaling the end of a phase in response to a phase done condition being satisfied.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: July 17, 2007
    Assignee: International Business Machines Corporation
    Inventors: Robert Brian Likovich, Jr., Joseph David Mendenhall, John Christopher Morris, Robert James Reese, Chad Everett Winemiller
  • Patent number: 7237210
    Abstract: Methods, systems, and media for managing functional verification of a parameterizable design are disclosed. Embodiments include a system having a testbench configuration module adapted to configure a testbench, the testbench having testbench signals and one or more instantiated components having a plurality of ports of a generic design, where the testbench signals are wired to the plurality of ports. The testbench may also have one or more instantiated special components based on chip-specific versions of the design where the special components are wired to the same ports as the generic design. The system may also include a functional verification manager that, through a component module, observes values in the testbench and automatically configure a verification environment based on the observed values, including automatic insertion of checkers at different levels of hierarchy. The testbench may be a VHDL or Verilog testbench in some embodiments.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: June 26, 2007
    Assignee: International Business Machines Corporation
    Inventors: Robert Brian Likovich, Jr., Joseph David Mendenhall, John Christopher Morris, David Otero, Chad Everett Winemiller
  • Patent number: 7143414
    Abstract: Processor threads in a multi-processor system can concurrently lock multiple semaphores by providing a lock command which includes the semaphore value and a semaphore number. Each processor is allocated two or more addressable semaphore stores, each of which include a multi-bit field identifying the requested semaphore and a one bit field identifying the locked status of the requested semaphore. The semaphore number determines which of the allocated semaphore stores are to be used for processing the lock command.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: November 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Marco Heddes, Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich, Jr.
  • Patent number: 7089555
    Abstract: An ordered semaphore management subsystem and method for use in an application system which includes a plurality of processors competing for shared resources each of which is controlled by a unique semaphore. The subsystem generates an ordered semaphore field (OSF) corresponding to each processor in a linked list of processors and assigns one of four statuses to the OSF depending on the position the processor occupies in the linked list of processors competing for the shared resources. The four states are (1) semaphore head (SH); (2) behind semaphore head (BSH); (3) semaphore head behind (SHB); and (4) skip (Skip). Only the SH processor is allocated the semaphore when requested. A processor not in the SH state will be denied the semaphore even if is available to assure sequential access.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jean Louis Calvignac, Gordon Taylor Davis, Marco Heddes, Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich, Jr.
  • Patent number: 6876664
    Abstract: An improved asynchronous data buffer is disclosed. The data buffer comprises an entry section and a signaling circuit coupled to the entry section, the signaling circuit for signaling the data buffer to transfer a portion of a data cell from the entry section prior to the data cell being completely received by the entry section. Through the use of the data buffer in accordance with the present invention, data transfer systems are improved in two ways. Firsts by enabling data to be transferred before it is completely stored into the buffer, the latency that is typically required for data cell transfer is reduced. Second, the buffer storage space that is typically required to store a complete data cell is also reduced. This twofold improvement produces increased data transfer rates while decreasing the amount of required buffer storage space.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: April 5, 2005
    Assignee: International Business Machines Corporation
    Inventors: Bryan Keith Bullis, John Charles Goss, Robert Brian Likovich, Jr.
  • Patent number: 6816829
    Abstract: The present invention describes a system and method for independently verifying the Execution Rate of individual tasks by a device through simulation. Described is a situation in which a system has a main device through which data flows to and from other devices. Bus transfers must fall within required rates. A simulation of the configuration utilizes models of the various devices, including the “Main device”. This simulation is used to verify the data traffic and associated transfer rates. Data transfer includes random bursts, with randomly chosen periods between bursts. The data rate and data validity are measured during each burst period.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Robert Franklin Clark, Robert Brian Likovich, Jr., Darryl Jonathan Rumph, Chad Everett Winemiller
  • Patent number: 6643257
    Abstract: A method of and program for dynamically testing a buffering and selection device, wherein the buffering and selection device receives a transmission at an average bandwidth of T and in peak bandwidth bursts that may be greater than T, are provided. The buffering and selection device transmits data to one or more receive devices, all of which have a total average bandwidth of at least T. The buffering and selection device has buffers apportioned to each receive device in order to store data that is written in burst mode destined for that receive device. The method includes disabling the output data flow to the receive device being tested and then generating input data to the buffering and selection device tagged for each receive device in burst mode at a preselected number of transfers for each receive device. The program determines when the preselected number of transfers has occurred and then enables data flow to the receive device being tested.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: November 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert Brian Likovich, Jr., Darryl Jonathan Rumph, Chad Everett Winemiller
  • Publication number: 20030060898
    Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.
    Type: Application
    Filed: September 19, 2002
    Publication date: March 27, 2003
    Applicant: International Business Machines Corporation
    Inventors: Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich, Wesley Erich Queen, Michael Steven Siegel
  • Publication number: 20030061259
    Abstract: Processor threads in a multi-processor system can concurrently lock multiple semaphores by providing a lock command which includes the semaphore value and a semaphore number. Each processor is allocated two or more addressable semaphore stores, each of which include a multi-bit field identifying the requested semaphore and a one bit field identifying the locked status of the requested semaphore. The semaphore number determines which of the allocated semaphore stores are to be used for processing the lock command.
    Type: Application
    Filed: September 19, 2002
    Publication date: March 27, 2003
    Applicant: International Business Machines Corporation
    Inventors: Marco Heddes, Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich
  • Publication number: 20030002440
    Abstract: An ordered semaphore management subsystem and method for use in an application system which includes a plurality of processors competing for shared resources each of which is controlled by a unique semaphore. The subsystem generates an ordered semaphore field (OSF) corresponding to each processor in a linked list of processors and assigns one of four statuses to the OSF depending on the position the processor occupies in the linked list of processors competing for the shared resources. The four states are (1) semaphore head (SH); (2) behind semaphore head (BSH); (3) semaphore head behind (SHB); and (4) skip (Skip). Only the SH processor is allocated the semaphore when requested. A processor not in the SH state will be denied the semaphore even if is available to assure sequential access.
    Type: Application
    Filed: June 25, 2002
    Publication date: January 2, 2003
    Applicant: International Business Machines Corporation
    Inventors: Jean Louis Calvignac, Gordon Taylor Davis, Marco Heddes, Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich
  • Publication number: 20030005195
    Abstract: A generic method and apparatus for managing semaphores in a multi-threaded processing system has a storage area for each of the threads in the processing system. Each storage area includes a first part for storing at least one indicia for identifying at least one unique semaphore from a plurality of semaphores utilized by the multi-threaded processing system and a second part for storing an indicia for indicating a locked status for the stored semaphore. A thread requiring a semaphore sends a semaphore lock request to the semaphore manager which examines the contents of all of the storage areas to determine the status of the requested semaphore. If the requested semaphore is not locked, it is locked for the requesting thread by inserting the requested semaphore and locked status in the memory location assigned to the requesting thread.
    Type: Application
    Filed: June 25, 2002
    Publication date: January 2, 2003
    Applicant: International Business Machines Corporation
    Inventors: Gordon Taylor Davis, Marco Heddes, Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich