Patents by Inventor Robert Broberg

Robert Broberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7570583
    Abstract: The invention provides a method and system for coupling a SONET/SDH network to a routing network that does not have a single point of failure. Multiple routers are coupled between the SONET/SDH network and the routing network, one for each data path; for example, a first router for the working data path and a second router for the protection data path. The routers intercommunicate to force APS to switch data paths bidirectionally, so as to allow only a single router for each data path.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: August 4, 2009
    Assignee: Cisco Technology, Inc.
    Inventors: Robert Broberg, David A. Getchell
  • Publication number: 20060112376
    Abstract: A computer-aided circuit design application has a virtual node feature and a design tool. The virtual node feature is adapted to access design specification information in a first data format and to represent the accessed design specification information as a virtual data node object within a list of node objects in a second data format. The design tool is operable on the list of node objects and the virtual data node object.
    Type: Application
    Filed: November 23, 2004
    Publication date: May 25, 2006
    Applicant: LSI Logic Corporation
    Inventors: Robert Broberg, George Nation
  • Publication number: 20060072595
    Abstract: An apparatus for charging in a network environment is provided that includes an access gateway encapsulation/decapsulation element operable to establish one or more packet data protocol (PDP) links on behalf of an end user and to perform encapsulation and decapsulation operations for one or more of the links associated with the end user. The access gateway encapsulation/decapsulation element is further operable to interface with a client services packet gateway (CSPG) that is operable to provide enhanced packet processing for the end user for requested information. The apparatus also includes an access gateway policy element operable to interface with the CSPG. The access gateway encapsulation/decapsulation element and the access gateway policy element cooperate to use one or more inter-module headers in order to coordinate the enhanced packet processing for one or more communication flows associated with the end user.
    Type: Application
    Filed: October 5, 2004
    Publication date: April 6, 2006
    Inventors: Robert Broberg, Mark Grayson, Louis Menditto, Rafael Montalvo, Chris O'Rourke, Timothy Stammers, Marco Centemeri, Jayaraman Iyer
  • Publication number: 20060072573
    Abstract: An apparatus for charging in a network environment is provided that includes an access gateway encapsulation/decapsulation element operable to establish one or more packet data protocol (PDP) links on behalf of an end user and to perform encapsulation and decapsulation operations for one or more of the links associated with the end user. The access gateway encapsulation/decapsulation element is further operable to interface with a client services packet gateway (CSPG) that is operable to provide enhanced packet processing for the end user for requested information. The apparatus also includes an access gateway policy element operable to interface with the CSPG. The access gateway encapsulation/decapsulation element and the access gateway policy element cooperate to use one or more inter-module headers in order to coordinate the enhanced packet processing for one or more communication flows associated with the end user.
    Type: Application
    Filed: October 28, 2004
    Publication date: April 6, 2006
    Inventors: Robert Broberg, Mark Grayson, Louis Menditto, Rafael Montalvo, Chris O'Rourke, Timothy Stammers, Marco Centemeri, Jayaraman Iyer
  • Publication number: 20050240892
    Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.
    Type: Application
    Filed: June 18, 2005
    Publication date: October 27, 2005
    Applicant: LSI LOGIC CORPORATION
    Inventors: Robert Broberg, Jonathan Byrn, Gary Delp, Michael Eneboe, Gary McClannahan, George Nation, Paul Reuland, Thomas Sandoval, Matthew Wingren
  • Publication number: 20050141415
    Abstract: The invention provides a method and system for coupling a SONET/SDH network to a routing network that does not have a single point of failure. Multiple routers are coupled between the SONET/SDH network and the routing network, one for each data path; for example, a first router for the working data path and a second router for the protection data path. The routers intercommunicate to force APS to switch data paths bidirectionally, so as to allow only a single router for each data path.
    Type: Application
    Filed: February 15, 2005
    Publication date: June 30, 2005
    Applicant: Cisco Technology, Inc., a California corporation
    Inventors: Robert Broberg, David Getchell
  • Publication number: 20050022155
    Abstract: File paths for a plurality of IC design files in a hardware description language are abstracted by parsing description files, or a directory of description file names, to identify file paths to each of the plurality of design files in a first environment. An index is generated correlating each design file and its respective file path. In use, a file path in a second environment of an application is defined for each design file, and the index is applied to the file paths in the second environment to define full file paths for each design file through the first and second environments. The design files are then applied to the application using the full file paths.
    Type: Application
    Filed: December 1, 2003
    Publication date: January 27, 2005
    Applicant: LSI Logic Corporation
    Inventors: Robert Broberg, John Reddersen, Judy Gehman