Patents by Inventor Robert Bruce Nicholson

Robert Bruce Nicholson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070101085
    Abstract: A copy engine (104) is provided as an interface between firmware (108) and memory space (106) for carrying out copy operations. The copy engine has a first register (202, 203) to point to a first address and a second register (204, 205) to point to a second address. One of the first and second addresses is a source address and one is a destination address for data to be copied. The copy engine (104) also has a control register (201). The control register (201) includes a count of the amount of memory space required by a copy operation, an indication of the direction of the copy operation from the first address to the second address or from the second address to the first address, and an indication of whether the first memory address is incremented or decremented. The copy engine (104) includes a locking mechanism for locking the copy engine (104) during a copy operation. The copy engine (104) also includes a serialisation mechanism in which a write is made to the control register (201) of zero count.
    Type: Application
    Filed: November 13, 2006
    Publication date: May 3, 2007
    Inventors: Carlos Francisco Fuente, Ian David Judd, Robert Bruce Nicholson, Mandy Stevens
  • Patent number: 7203161
    Abstract: A method and apparatus for recovery from faults in a loop network (500) is provided. The loop network (500) has a plurality of ports (520, 530, 532, 534) serially connected with means for bypassing the ports (520, 530, 532, 534) from the loop network (500). A control device (522, 524) is provided with bypass control over at least one of the ports (530, 532, 534). A host means (502) sends a command to the control device (522, 524) at regular intervals and the control device (522, 524) has a counter which restarts a time period at the receipt of each command. If the time period expires, the control device (522, 524) activates the means for bypassing all the ports (530, 532, 534) under its control. The loop network (500) may have two loops (516, 518) with at least some of the ports (520, 530, 532, 534) common to both loops (516, 518).
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: April 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Robert Bruce Nicholson, Barry Douglas Whyte
  • Patent number: 7200108
    Abstract: A method and apparatus for recovery from faults in a loop network (400) is provided. The loop network (400) has a host means (402), a first loop and a second loop (406, 408), a plurality of ports (410) connected to each of the loops (406, 408) and a control device (414, 440) on or connected to each loop (406, 408) with bypass control over at least one of the ports (410) connected to the loop (406, 408). In the event of a failure on the first loop (406), the host means (402) instructs the bypassing of at least one port (410) on the first loop (406), the host means (402) sending the instructions via the control device (414, 440) on or connected to the second loop (408).
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: April 3, 2007
    Assignee: International Business Machines Corporation
    Inventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Neil Morris, Robert Bruce Nicholson, Barry Douglas Whyte
  • Patent number: 7136979
    Abstract: A copy engine (104) is provided as an interface between firmware (108) and memory space (106) for carrying out copy operations. The copy engine has a first register (202, 203) to point to a first address and a second register (204, 205) to point to a second address. One of the first and second addresses is a source address and one is a destination address for data to be copied. The copy engine (104) also has a control register (201). The control register (201) includes a count of the amount of memory space required by a copy operation, an indication of the direction of the copy operation from the first address to the second address or from the second address to the first address, and an indication of whether the first memory address is incremented or decremented. The copy engine (104) includes a locking mechanism for locking the copy engine (104) during a copy operation. The copy engine (104) also includes a serialisation mechanism in which a write is made to the control register (201) of zero count.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: November 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Carlos Francisco Fuente, Ian David Judd, Robert Bruce Nicholson, Mandy A Stevens
  • Patent number: 7117320
    Abstract: A method for maintaining data access during failure of a controller in a multiple controller storage subsystem (103) is provided. The storage subsystem (103) has an array of data storage devices (109) and more than one controller (104, 105) for managing the data storage. The method comprises a first controller (201) saving its internal state information (212) and, optionally, resetting itself (213). One or more of the other controllers (202, 203) carry out the steps of pausing operation of the controller (221, 231), saving internal state information of the controller at the time of pausing (222, 232), and continuing operation of the controller (223, 233). The one or more other controllers (202, 203) may pause operation and save their internal state information when they receive a message broadcast (220, 230) from the first controller (201) which has detected an error.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: October 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Paul Ashmore, Matthew John Fairhurst, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh, Barry John Wood
  • Patent number: 7080208
    Abstract: A method for data retention in a data cache and a data storage system are provided. The data storage system (100) includes a storage controller (102) with a cache (103) and a data storage means (106). The cache (103) has a first least recently used list (104) for referencing dirty data which is stored in the cache (103), and a second least recently used list (105) for clean data in the cache (103). Dirty data is destaged from the cache (103) when it reaches the tail of the first least recently used list (104) and clean data is purged from the cache (103) when it reaches the tail of the second least recently used list (105).
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Paul Ashmore, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh
  • Patent number: 6993627
    Abstract: A data storage system (100) and a method of storing data are described including a cache (118) with a variable number of levels (210, 220, 230, 240). Each level in the cache (118) has a cache controller (212, 222, 232, 242) and a cache memory (214, 224, 234, 244) for storing data. An address mapping is recorded and applied between each of the levels of the cache (118). The address mapping corresponds to a point in time virtual copy operation such as a snapshot copy operation applied to the cache (118) and enables point in time virtual copy operations to be carried out in electronic time. A new level is created in the cache (118) when a point in time virtual copy operation is received by the cache and a corresponding address mapping is applied to the previous level in the cache (118).
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: January 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Henry Esmond Butterworth, Robert Bruce Nicholson
  • Patent number: 6954882
    Abstract: A method and apparatus are provided for fault location in a loop network (100, 200, 400). The network system having a host port (214) for supplying and receiving data and a plurality of successively connected ports (201, 202, 203, 204, 205) through which data from the host port (214) is transferred. A counter (122) for each port records data transfers in which the amount of data received at a destination port is less than an expected amount of data. When a transfer with less than the expected amount of data is identified for a data flow between a sending port (201) and a destination port (214), the counters are incremented for each port (202, 203, 204, 205, 214) after the sending port up to and including the destination port. Analysing means determines a fault location in the network system from the distribution of counts in the counters (122).
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: October 11, 2005
    Assignee: International Business Machines Corporation
    Inventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Neil Morris, Robert Bruce Nicholson, Barry Douglas Whyte
  • Patent number: 6941420
    Abstract: A log structured array (LSA) controller apparatus controls the transfer of information between a processor and a plurality of information storage devices configured as an N+1 array in which the information is stored as stripes extending across the devices of the array, each stripe comprising N information strips and one parity strip, each information strip storing an integer number of logical tracks. The controller defines an LSA directory that specifies the location of each logical track in terms of the ID of the stripe to which the track belongs and the offset of the track within the stripe; wherein on the addition of an information storage device to the array, the additional strip provided for each stripe by the storage device is logically appended to the end of each stripe in the LSA directory.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Henry Esmond Butterworth, Robert Bruce Nicholson, William James Scales, Douglas Turner
  • Patent number: 6907454
    Abstract: A data processing system comprises a master processor (10), a slave processor (30), a memory (50), and a bus subsystem (20) interconnecting the master processor (10), the slave processor (30), and the memory (50). The master processor (10) is configured to generate, in response to a memory access instruction, a read request comprising a read command for execution by the slave processor (30) to read data stored in a location in the memory (50) specified by the memory access instruction, and to write the read request to the slave processor (30) via the bus subsystem (20). The slave processor (30) is configured to execute the read command received in the read request from the master processor (10) to obtain the data stored at the specified location in the memory (50) and to write the data thus obtained to the master processor (10) via the bus subsystem (20).
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventors: Henry Esmond Butterworth, Carlos Francisco Fuente, Robert Bruce Nicholson
  • Patent number: 6738863
    Abstract: A method for rebuilding meta-data stored in a data storage system (104) having storage devices (106) in which segments of data are located; for example, a storage system in the form of a log structured array. Data is written in segments to the storage devices (106) from a plurality of flows (122) of data and each segment of data contains meta-data relating to that segment. The meta-data stored in the storage system (104) can be rebuilt in the event of a failure by scanning the meta-data in each segment. A first scan of the meta-data in each segment in the storage devices (106) identifies the last segment written from each flow (122) and these segments are excluded from the rebuilding process as they may contain incomplete or inconsistent information. A second scan of the meta-data in each segment in the storage devices (106) identifies any segments which do not contain any live data tracks and these segments are also excluded from the, rebuilding process.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: May 18, 2004
    Assignee: International Business Machines Corporation
    Inventors: Henry Esmond Butterworth, Robert Bruce Nicholson
  • Publication number: 20040093468
    Abstract: An arrangement and method for update of configuration cache data in a disk storage subsystem in which a cache memory (110) is updated using two-phase (220, 250) commit technique.
    Type: Application
    Filed: June 20, 2003
    Publication date: May 13, 2004
    Applicant: International Business Machines Corporation
    Inventors: David John Carr, Michael John Jones, Andrew Key, Robert Bruce Nicholson, William James Scales, Barry Douglas Whyte
  • Publication number: 20040049638
    Abstract: A method for data retention in a data cache and a data storage system are provided. The data storage system (100) includes a storage controller (102) with a cache (103) and a data storage means (106). The cache (103) has a first least recently used list (104) for referencing dirty data which is stored in the cache (103), and a second least recently used list (105) for clean data in the cache (103). Dirty data is destaged from the cache (103) when it reaches the tail of the first least recently used list (104) and clean data is purged from the cache (103) when it reaches the tail of the second least recently used list (105).
    Type: Application
    Filed: August 6, 2003
    Publication date: March 11, 2004
    Applicant: International Business Machines Corporation
    Inventors: Paul Ashmore, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh
  • Publication number: 20040049710
    Abstract: A method for maintaining data access during failure of a controller in a multiple controller storage subsystem (103) is provided. The storage subsystem (103) has an array of data storage devices (109) and more than one controller (104, 105) for managing the data storage. The method comprises a first controller (201) saving its internal state information (212) and, optionally, resetting itself (213). One or more of the other controllers (202, 203) carry out the steps of pausing operation of the controller (221, 231), saving internal state information of the controller at the time of pausing (222, 232), and continuing operation of the controller (223, 233). The one or more other controllers (202, 203) may pause operation and save their internal state information when they receive a message broadcast (220, 230) from the first controller (201) which has detected an error.
    Type: Application
    Filed: June 26, 2003
    Publication date: March 11, 2004
    Applicant: International Business Machines Corporation
    Inventors: Paul Ashmore, John Matthew Fairhurst, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh, Barry John Wood
  • Patent number: 6704839
    Abstract: A data storage system and method of storing data with at least two controllers (200, 300) which share a storage space (244, 344) on an array of storage devices and which support the same set of logical upstream devices. The controllers (200, 300) share the workload by dividing the shared storage space (244, 344) into stripes where the stripes are sufficiently small to divide the workload uniformly across the storage device. This is achieved in the case of two controllers (200, 300) of a log structured array by dividing the storage space into odd and even tracks, all odd tracks being designated to one controller (300) and all even tracks to the other controller (200).
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: March 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Henry Esmond Butterworth, Robert Bruce Nicholson, Douglas Turner
  • Publication number: 20030140099
    Abstract: A method and apparatus are provided for hard address conflict resolution for enclosures in a loop network (200). The loop network (200) has: a loop (202); a host means (201) on or connected to the loop (202); a plurality of devices (207) on or connected to the loop (202); and at least one enclosure containing one or more devices (207). Each device (207) has an address means. Each enclosure has an enclosure control device (208) with control over devices (207) in that enclosure. Each enclosure control device (208) has an address means. The method includes, at the start up of the loop network (200), setting the address means of the enclosure control devices (208) to a default value. Each device (207) is then entered in the loop (202) in a reset state in which only the enclosure control devices (208) and the host means (201) are active in the loop (202).
    Type: Application
    Filed: November 8, 2002
    Publication date: July 24, 2003
    Applicant: International Business Machines Corporation
    Inventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Neil Morris, Robert Bruce Nicholson, Paul Jonathan Quelch, Barry Douglas White
  • Publication number: 20030137987
    Abstract: A method and apparatus for detection of a port name in a loop network is provided, particularly a loop network in the form of a Fibre Channel Arbitrated Loop (FC-AL). The loop network (100) has a plurality of devices (120) each device (120) having at least one port (211, 212) on the loop network (100). The method includes determining which ports (211, 212) are populated with devices (120) for which the unique port name (WWPN) is not known. The populated ports are then all bypassed and a mode is entered on the loop network (100) in which idle frames are transmitted around the loop network (100). One port is un-bypassed at a time and the port name from the un-bypassed port is received and recorded. The port name is received from the un-bypassed port in a Loop Initialisation Select Master (LISM) frame transmitted by the un-bypassed port.
    Type: Application
    Filed: November 8, 2002
    Publication date: July 24, 2003
    Applicant: International Business Machines Corporation
    Inventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Neil Morris, Robert Frank Maddock, Robert Bruce Nicholson
  • Publication number: 20030140277
    Abstract: A method and apparatus for relating a device name to a physical location of a device (202) on a network is provided. The network may be a serial loop network, for example a Fibre Channel Arbitrated Loop network. The network includes a plurality of devices (202) on or connected to the network (201) and a control device (205) with control over at least one of the devices (202). Each device (202) has a check output (204) independent of the network (201) with connection means (206) to a control device (205). The method includes the step of sending a device name from the check output (204) of a device (202) to the control device (205). The check output (204) of a device (202) is also connected to an external indication means for indicating the failure of the device (202).
    Type: Application
    Filed: November 8, 2002
    Publication date: July 24, 2003
    Applicant: International Business Machines Corporation
    Inventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Neil Morris, Robert Bruce Nicholson, Paul Jonathan Quelch, Barry Douglas White
  • Publication number: 20030056153
    Abstract: A method and apparatus are provided for fault location in a loop network (100, 200, 400). The network system having a host port (214) for supplying and receiving data and a plurality of successively connected ports (201, 202, 203, 204, 205) through which data from the host port (214) is transferred. A counter (122) for each port records data transfers in which the amount of data received at a destination port is less than an expected amount of data; When a transfer with less than the expected amount of data is identified for a data flow between a sending port (201) and a destination port (214), the counters are incremented for each port (202, 203, 204, 205, 214) after the sending port up to and including the destination port. Analysing means determines a fault location in the network system from the distribution of counts in the counters (122).
    Type: Application
    Filed: June 14, 2002
    Publication date: March 20, 2003
    Applicant: International Business Machines Corporation
    Inventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Neil Morris, Robert Bruce Nicholson, Barry Douglas Whyte
  • Publication number: 20030031163
    Abstract: A method and apparatus for improving performance of a loop network, in particular a Fiber Channel Arbitrated Loop. The loop network has two loops and a plurality of dual-ported devices each with one port on each loop. The method includes selectively bypassing redundant ports on the loops by a first command means in the form of a Fiber Channel Arbitrated Loop command to balance port accesses and to reduce the loop overhead by reducing the number of ports in each loop. In the event of a fault, bypassing the port of a device by a second command means in the form of a non Fiber Channel Arbitrated Loop command and enabling all the bypassed redundant ports with a single command to all ports using the first command means. The first command means does not enable the port bypassed by the second command means.
    Type: Application
    Filed: August 6, 2002
    Publication date: February 13, 2003
    Inventors: Paul Nicholas Cashman, Robert Frank Maddock, Robert Bruce Nicholson, Michael Alan Veal