Abstract: In an environment wherein a microprocessor can operate at several different voltage levels depending upon the instantaneous throughput of the microprocessor, a memory and memory adjustment circuit that permits operating the memory at a plurality of voltages in response to the microprocessor is disclosed. The memory and memory adjustment circuit sense the instantaneous operating voltage of the microprocessor and adjust the operating voltage of the memory in response thereto. The memory adjustment circuit more particularly increases or decreases the memory's bitline sense interval in response respectively to a decrease or increase in the memory's operating voltage.

Abstract: A method and system for generating a synchronous sequence of vectors from information originating within an asynchronous environment is disclosed. A simulated asynchronous sequence is synchronized by extracting a state at each clock period to generate a simulation synchronous sequence. This sequence is manipulated first to include short delays for generating an asynchronous short-delay sequence and second to include long delays for generating an asynchronous long-delay sequence. An overlay is separately performed among the clock periods of the asynchronous short-delay sequence and the asynchronous long-delay sequence to respectively identify a first interval and a second interval. The first interval and the second interval are independently duplicated in successive clock periods to respectively generate a synchronous short-delay sequence and a synchronous long-delay sequence.

Abstract: A method and system for generating a synchronous sequence of vectors from information originating within an asynchronous environment is disclosed. A simulated asynchronous sequence is synchronized by extracting a state at each clock period to generate a simulation synchronous sequence. This sequence is manipulated first to include short delays for generating an asynchronous short-delay sequence and second to include long delays for generating an asynchronous long-delay sequence. An overlay is separately performed among the clock periods of the asynchronous short-delay sequence and the asynchronous long-delay sequence to respectively identify a first interval and a second interval. The first interval and the second interval are independently duplicated in successive clock periods to respectively generate a synchronous short-delay sequence and a synchronous long-delay sequence.

Abstract: An integrated circuit is provided with Fully Automated Scan Testing (FAST)-lite flip-flop. The integrated circuit has data, scan in, master-hold, clock, scan-into-master, and master to-scan-out inputs. A first transistor circuit is connected to the data, master-hold, and clock inputs and has a first transistor circuit output. A second transistor circuit is connected to the can in and scan-into-master inputs and has a second transistor circuit output. A first flip-flop is connected to the first transistor circuit and second transistor circuit outputs and has a first flip-flop output. A third transistor circuit is connected to the second transistor circuit output and the master-to-scan-out input and has a third transistor circuit output. A second flip-flop latch is connected to the third transistor circuit output has a second flip-flop output. The FAST-lite flip-flop uses the normal functionality of the first flip-flop and second flip-flop to operate either in a normal mode or a test mode for scan testing.

Abstract: An integrated circuit having an embedded testing system. The integrated circuit has a plurality of chip input terminals and a plurality of chip output terminals and operates in a test mode and a normal mode. The integrated circuit includes a plurality of core modules and a test data bus. The test data bus has first and second conductors accessible from the chip input and output terminals, respectively. Each core module includes an access register for storing an access word, and a plurality of registers connected together as a first scan-chain having an input terminal for receiving data to be shifted into the registers and an output terminal for reading data shifted out of the registers. Each core module also includes a scan-in enable circuit and a scan-out enable circuit. The scan-in enable circuit connects the input terminal of the first scan-chain to the first conductor of the test data bus.