Abstract: The present invention is embodied in a memory system which restores full functionality to a dynamic random access main memory having at least one defective bit. In a preferred embodiment of the invention, the memory system is integrated on an industry standard memory module which is plugged into a host computer system. The memory module incorporates a block of DRAM main memory, an SRAM replacement memory, a non-volatile memory which stores a map of defective memory locations within the main memory, and a process control module (PCM) operable in multiple modes, which manages a defective address identification and replacement process. The PCM, which contains high-speed registers, in addition to decoding and control logic, is implemented as a high-speed application-specific integrated circuit (ASIC).