Abstract: An ESD protection arrangement for a silicon-on-insulator device has an N-well type implant in the silicon substrate of the device, a p.sup.+ implant forming a juncture with the N-well type implant, and an n.sup.+ implant defining a juncture with the N-well type implant, in order to protect against negative transients and positive transients. At the p-channel threshold adjust, both the p-channel of the device and the N-well are implanted. Implanting the N-well to a depth of about 0.15 to about 0.30 .mu.m provides suitable characteristics for both the N-well and the p-channel.