Patents by Inventor Robert C. Byrne

Robert C. Byrne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5369299
    Abstract: A tamper resistant structure has a pattern which covers portions of an IC but exposes other portions of the IC so that etching away the tamper resistant structure destroys the exposed portions. The IC can not be easily disassembled and reverse engineered because the tamper resistant structure hides active circuitry and removing the tamper resistant structure destroys active circuitry. One embodiment of the tamper resistant structure includes a metal layer and a cap layer. The cap layer typically includes material that is difficult to remove, such as silicon carbide, silicon nitride, or aluminum nitride. The metal layer typically includes a chemically resistant material such as gold or platinum. A bonding layer of nickel-vanadium alloy, titanium-tungsten alloy, chromium, or molybdenum, may be used to provide stronger bonds between layers. Some embodiments provide an anti-corrosion seals for bonding pads in addition to the tamper residant structure.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: November 29, 1994
    Assignee: National Semiconductor Corporation
    Inventor: Robert C. Byrne
  • Patent number: 5136364
    Abstract: Integrated circuit bonding pads are sealed by a surface passivation coating. The bonding pads are first edge-sealed by means of a first applied passivation coating that overlaps the edges of the bonding pad while leaving the central area uncoated. Then, a sequence of metal layers applied to overlap the open central area of the bonding pad. The layer sequence includes an optional first adherence layer such as aluminum, a barrier metal layer such as titanium-tungsten alloy, and an outer noble metal layer such as gold. Then, a second passivation layer is applied so as to overlap and seal the edges of the sequence of metal layers so as to leave only the central portion of the noble metal layer exposed. Electrical contact to the IC is then made to the exposed noble metal in the conventional manner. With respect to the passivating coatings, either or both can be silicon dioxide overcoated with silicon nitride.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: August 4, 1992
    Assignee: National Semiconductor Corporation
    Inventor: Robert C. Byrne
  • Patent number: 4833102
    Abstract: A sidebrazed ceramic package is provided with a closure seal that employs a high alumina ceramic lid that matches the composition of the package body. The lid is provided with a recess in the sealing face and the sealing face is provided with metallization that adheres to the ceramic and is wet by solder. The metallized ceramic lid is sealed to the metallization ring on the sidebrazed ceramic body by means of the conventional gold-tin solder. The resultant hermetic seal can be inspected by observing the solder fillet in the lid recess. Such a closure seal is fully hermetic and can readily survive repeated thermal cycling.
    Type: Grant
    Filed: June 9, 1988
    Date of Patent: May 23, 1989
    Assignee: National Semiconductor Corporation
    Inventors: Robert C. Byrne, Jon T. Ewanich, Chee-Men Yu
  • Patent number: 4769272
    Abstract: A sidebrazed ceramic package is provided with a closure seal that employs a high alumina ceramic lid that matches the composition of the package body. The lid is provided with a recess in the sealing face and the sealing face is provided with metallization that adheres to the ceramic and is wet by solder. The metallized ceramic lid is sealed to the metallization ring on the sidebrazed ceramic body by means of the conventional gold-tin solder. The resultant hermetic seal can be insepcted by observing the solder fillet in the lid recess. Such a closure seal is fully hermetic and can readily survive repeated thermal cycling.
    Type: Grant
    Filed: March 17, 1987
    Date of Patent: September 6, 1988
    Assignee: National Semiconductor Corporation
    Inventors: Robert C. Byrne, Jon T. Ewanich, Chee-Men Yu