Patents by Inventor Robert C. Frye

Robert C. Frye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973629
    Abstract: A method of calibrating a transmitter chain in a phased array system in which a lower guard band is assigned to a lower side of an operating carrier of a communication channel and an upper guard band is assigned an upper side of the operating carrier includes injecting a first calibration tone into the transmitter chain and detecting its arrival at the end of the transmitter chain, at which point a first detected calibration signal is generated. The first detected calibration signal and the injected first calibration tone are then compared to produce a first comparison signal. The transmitter chain's phase and/or gain is then adjusted based on this first comparison signal. The first calibration tone located within one of the lower and upper guard bands of the communication channel of the transmitter chain.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: April 30, 2024
    Assignee: NEC Advanced Networks, Inc.
    Inventors: Gregg S. Nardozza, Giovanni Marzin, Yiping Feng, Robert C. Frye, Mihai Banu
  • Publication number: 20230106538
    Abstract: A method of calibrating a transmitter chain in a phased array system in which a lower guard band is assigned to a lower side of an operating carrier of a communication channel and an upper guard band is assigned an upper side of the operating carrier includes injecting a first calibration tone into the transmitter chain and detecting its arrival at the end of the transmitter chain, at which point a first detected calibration signal is generated. The first detected calibration signal and the injected first calibration tone are then compared to produce a first comparison signal. The transmitter chain's phase and/or gain is then adjusted based on this first comparison signal. The first calibration tone located within one of the lower and upper guard bands of the communication channel of the transmitter chain.
    Type: Application
    Filed: October 4, 2022
    Publication date: April 6, 2023
    Inventors: Gregg S. Nardozza, Giovanni Marzin, Yiping Feng, Robert C. Frye, Mihai Banu
  • Patent number: 10693221
    Abstract: A removable module for a phased array, the module including: a circuit board having a ground plane formed on one side of the circuit board; an antenna mounted on and extending away from a topside of the circuit board; circuitry on a backside of the circuit board, the circuitry including an RF front end circuit coupled to the antenna; and a group of one or more first connecters mounted on the backside of the circuit board, the first connectors for physically and electrically connecting and disconnecting the module from a master board through a corresponding group of one or more matching second connectors on the master board, the first connectors on the module having electrically conductive lines for carrying an externally supplied LO signal for the RF front end circuit and an IF signal for or from the RF front end circuit.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: June 23, 2020
    Assignee: Blue Danube Systems, Inc.
    Inventors: Robert C. Frye, Peter Kiss, Josef Ocenasek
  • Patent number: 10181943
    Abstract: A method involving a serial interconnection system having a first node, a second node, a plurality of calibration nodes that are electrically connected in series by the serial interconnection system, and a plurality of connection nodes corresponding to the plurality of serially connected calibration nodes and electrically connected in series by the serial interconnection system, the method involving: for each of the plurality of calibration nodes performing a measurement procedure involving: injecting a corresponding reference signal into that calibration node; and while the corresponding reference signal is being injected into that calibration node, determining a summation of the phases of signals appearing at the first and second nodes; from the determined phase summations for the plurality of calibration nodes, computing phase corrections for each of the plurality of calibration nodes; and applying the phase corrections to the corresponding plurality of connection nodes.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: January 15, 2019
    Assignee: Blue Danube Systems, Inc.
    Inventors: Robert C. Frye, Mihai Banu
  • Publication number: 20180091292
    Abstract: A method involving a serial interconnection system having a first node, a second node, a plurality of calibration nodes that are electrically connected in series by the serial interconnection system, and a plurality of connection nodes corresponding to the plurality of serially connected calibration nodes and electrically connected in series by the serial interconnection system, the method involving: for each of the plurality of calibration nodes performing a measurement procedure involving: injecting a corresponding reference signal into that calibration node; and while the corresponding reference signal is being injected into that calibration node, determining a summation of the phases of signals appearing at the first and second nodes; from the determined phase summations for the plurality of calibration nodes, computing phase corrections for each of the plurality of calibration nodes; and applying the phase corrections to the corresponding plurality of connection nodes.
    Type: Application
    Filed: April 13, 2017
    Publication date: March 29, 2018
    Inventors: Robert C. Frye, Mihai Banu
  • Patent number: 9653768
    Abstract: A signal distribution structure including: a dielectric material; an overlying conducting layer on a first level of the dielectric material; a first signal line on a second level of the dielectric material, the first signal line being physically separated from the overlying conducting layer by the dielectric material; wherein the overlying conducting layer includes a window running parallel to the first signal line, and further comprising within the window a first coupler electrode on the first level of the dielectric material, the first coupler electrode above, parallel to, and electrically isolated by the dielectric material from the first signal line, wherein the first coupler electrode is electrically isolated from the overlying conducting layer along at least most of its periphery.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 16, 2017
    Assignee: Blue Danube Systems, Inc.
    Inventor: Robert C. Frye
  • Publication number: 20170025749
    Abstract: A removable module for a phased array, the module including: a circuit board having a ground plane formed on one side of the circuit board; an antenna mounted on and extending away from a topside of the circuit board; circuitry on a backside of the circuit board, the circuitry including an RF front end circuit coupled to the antenna; and a group of one or more first connecters mounted on the backside of the circuit board, the first connectors for physically and electrically connecting and disconnecting the module from a master board through a corresponding group of one or more matching second connectors on the master board, the first connectors on the module having electrically conductive lines for carrying an externally supplied LO signal for the RF front end circuit and an IF signal for or from the RF front end circuit.
    Type: Application
    Filed: July 21, 2016
    Publication date: January 26, 2017
    Inventors: Robert C. Frye, Peter Kiss, Josef Ocenasek
  • Patent number: 9484334
    Abstract: A semiconductor device has a substrate and RF coupler formed over the substrate. The RF coupler has a first conductive trace with a first end coupled to a first terminal of the semiconductor device, and a second conductive trace with a first end coupled to a second terminal of the semiconductor device. The first conductive trace is placed in proximity to a first portion of the second conductive trace. An integrated passive device is formed over the substrate. A second portion of the second conductive trace operates as a circuit component of the integrated passive device. The integrated passive device can be a balun or low-pass filter. The RF coupler also has a first capacitor coupled to the first terminal of the semiconductor device, and second capacitor coupled to a third terminal of the semiconductor device for higher directivity. The second conductive trace is wound to exhibit an inductive property.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: November 1, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Robert C. Frye, Kai Liu
  • Patent number: 9349723
    Abstract: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the insulating layer. The passive device is a metal-insulator-metal capacitor. The deposition of the insulating layer and first and second conductive layers is performed without photolithography. An under bump metallization (UBM) layer is formed on the substrate in electrical contact with the plurality of active devices. A solder bump is formed over the UBM layer. The passive device can also be a resistor by depositing a resistive layer over the first conductive layer and depositing a third conductive layer over the resistive layer. The passive device electrically contacts the solder bump.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: May 24, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Qing Zhang, Robert C. Frye
  • Patent number: 9343396
    Abstract: A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: May 17, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Robert C. Frye, Pandi Chelvam Marimuthu, Kai Liu
  • Publication number: 20150372366
    Abstract: A signal distribution structure including: a dielectric material; an overlying conducting layer on a first level of the dielectric material; a first signal line on a second level of the dielectric material, the first signal line being physically separated from the overlying conducting layer by the dielectric material; wherein the overlying conducting layer includes a window running parallel to the first signal line, and further comprising within the window a first coupler electrode on the first level of the dielectric material, the first coupler electrode above, parallel to, and electrically isolated by the dielectric material from the first signal line, wherein the first coupler electrode is electrically isolated from the overlying conducting layer along at least most of its periphery.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 24, 2015
    Inventor: Robert C. Frye
  • Publication number: 20150373837
    Abstract: A signal transmission system including first and second transmission lines laid out side by side on a planar surface over a length L, each transmission line including a first conducting path and a second conducting path and each transmission line including a plurality of crossover structures at each of which the first and second conducting paths of that transmission line cross over each other to reverse the position of the two conducting paths relative to each other, wherein the plurality of crossover structures on the two transmission lines are arranged over the length L of the two transmission lines such that each of the first and second conducting paths of the first transmission line is a nearest neighbor of each of the first and second conducting paths of the second transmission line over distances that are substantially the same.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 24, 2015
    Inventor: Robert C. Frye
  • Patent number: 9171797
    Abstract: A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: October 27, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Robert C. Frye
  • Patent number: 8981866
    Abstract: A semiconductor device has an RF balun formed over a substrate. The RF balun includes a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device. A first capacitor is coupled between the first and second ends of the first conductive trace. A second conductive trace is wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device. The first conductive trace is formed completely within the second conductive trace. The first conductive trace and second conductive trace can have an oval, circular, or polygonal shape separated by 50 micrometers. A second capacitor is coupled between the first and second ends of the second conductive trace.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: March 17, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Robert C. Frye, Kai Liu
  • Patent number: 8975980
    Abstract: A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: March 10, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Kai Liu, Robert C. Frye, Yaojian Lin
  • Patent number: 8921127
    Abstract: A semiconductor device has a substrate and conductive layer over the substrate. A resistive element is formed between first and second portions of the conductive layer. A plurality of semiconductor die each with first and second bumps is mounted to the substrate with the first and second bumps electrically connected to the first and second portions of the conductive layer. A test current is routed in sequence through the first portion of the conductive layer, through the first and second bumps, and through the second portion of the conductive layer until continuity failure of the second bump. The test current originates from a single power supply. The test current continues to flow through the resistive element after the continuity failure of the second bump. The continuity failure can be detected by sensing an increase in voltage across the second bump.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: December 30, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Robert C. Frye, Kai Liu
  • Patent number: 8791775
    Abstract: A semiconductor device has a substrate and band-pass filter formed over the substrate. The band-pass filter includes a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device, and first capacitor coupled between the first and second ends of the first conductive trace. A second conductive trace is wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device. The second conductive trace has a different size and shape as the first conductive trace. A second capacitor is coupled between the first and second ends of the second conductive trace. A third conductive trace is wound around the first and second conductive traces to exhibit inductive properties.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: July 29, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Kai Liu, Robert C. Frye
  • Patent number: 8703548
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 22, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Robert C. Frye
  • Publication number: 20140002207
    Abstract: A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.
    Type: Application
    Filed: September 4, 2013
    Publication date: January 2, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Kai Liu, Robert C. Frye, Yaojian Lin
  • Patent number: 8576026
    Abstract: A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: November 5, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Kai Liu, Robert C. Frye, Yaojian Lin