Abstract: A process and structure are disclosed whereby dopants are used to surround crystalline defects in a semiconductor crystal thereby creating a PN junction which isolates the defect site from the remaining semiconductor substrate and preventing charge flow through the defect into the potential well of a charge coupled device structure.

Abstract: A dual gate MNOS memory transistor is disclosed. The transistor includes drain and source regions of a first conductivity type formed in a substrate of a second conductivity type. The region of the substrate between the drain and source regions forms the channel of the transistor. First and second insulating layers forming a charged trapping structure overlie the channel region. A first gate having a width less than the width of the channel overlies the central portion of the channel region. A second gate, insulated from the first gate, overlies the first gate and the remainder of the channel region. The threshold voltage of the transistor is shifted by selectively biasing the gates and the substrate. High and low threshold voltage states are used to represent the two values of a digital signal.