Abstract: A programmable resistor can provide discrete logarithmic (linear-in-dB) gain control. It can include multiple like programmable resistor subnetworks or cells, such as can be connected in parallel, such as according to a decoding scheme. The subnetworks can be configured to cover a subrange such as [0 dB, ?6 dB) relative to the maximum resistance value. Coarse increments of ?6 dB can be further added to this range by successively doubling the number of subnetworks that are connected in parallel. An additional decoder help ensure a linear control curve, free of dead zones or other nonlinearities. The programmable resistor can be suitable for use in such circuits as programmable-gain amplifiers, filters, or more complex networks, such as where the resistance can be programmed as a function of a digital code. An example including a tuning circuit for a variable gain active filter is described.

Abstract: A programmable resistor can provide discrete logarithmic (linear-in-dB) gain control. It can include multiple like programmable resistor subnetworks or cells, such as can be connected in parallel, such as according to a decoding scheme. The subnetworks can be configured to cover a subrange such as [0 dB, ?6 dB) relative to the maximum resistance value. Coarse increments of ?6 dB can be further added to this range by successively doubling the number of subnetworks that are connected in parallel. An additional decoder help ensure a linear control curve, free of dead zones or other nonlinearities. The programmable resistor can be suitable for use in such circuits as programmable-gain amplifiers, filters, or more complex networks, such as where the resistance can be programmed as a function of a digital code. An example including a tuning circuit for a variable gain active filter is described.

Abstract: Aspects of this disclosure relate to compensating for an offset in a receiver. In one embodiment, the receiver comprises a mixer, a feedback amplifier, and an offset correction circuit. The offset correction circuit can generate an indication of an offset in a differential input to the feedback amplifier and apply an offset compensation signal at an offset compensation node. The offset compensation node can be in a signal path of the feedback amplifier. Such offset compensation can reduce or eliminate leakage from a local oscillator at an input port of the mixer and/or at an antenna port of the receiver.

Abstract: Aspects of this disclosure relate to compensating for an offset in a receiver. In one embodiment, the receiver comprises a mixer, a feedback amplifier, and an offset correction circuit. The offset correction circuit can generate an indication of an offset in a differential input to the feedback amplifier and apply an offset compensation signal at an offset compensation node. The offset compensation node can be in a signal path of the feedback amplifier. Such offset compensation can reduce or eliminate leakage from a local oscillator at an input port of the mixer and/or at an antenna port of the receiver.

Abstract: Embodiments of the present invention may include a filter with programmable components, a tuning signal generator, a comparator, and a feedback system. The tuning signal generator may input first and second test signals into the filter and the comparator may sample the output of the filter in response to each respective signal. The comparator may then compare the sampled outputs to predetermined values. In response to the comparator's output, the feedback system may vary the programmable components of the filter until the search of the programmable components is exhausted, yielding first and second tuning results. Finally, the feedback system may determine a final tuning result based on the first and second tuning results. Consequently, the filter's actual corner frequency may be within an acceptable range of a desired corner frequency.

Abstract: Embodiments of the present invention may include a filter with programmable components, a tuning signal generator, a comparator, and a feedback system. The tuning signal generator may input first and second test signals into the filter and the comparator may sample the output of the filter in response to each respective signal. The comparator may then compare the sampled outputs to predetermined values. In response to the comparator's output, the feedback system may vary the programmable components of the filter until the search of the programmable components is exhausted, yielding first and second tuning results. Finally, the feedback system may determine a final tuning result based on the first and second tuning results. Consequently, the filter's actual corner frequency may be within an acceptable range of a desired corner frequency.

Abstract: Apparatus, systems and methods for image sensor leakage and dark current compensation are disclosed. In one implementation, a system comprises an imaging device including imaging pixels and two or more dark pixels, processing logic coupled to the imaging device, and an antenna coupled to the processing logic through an input/output (I/O) interface.

Abstract: An arrangement for generating control signals is provided. Embodiments provides a method, apparatus, system, and machine-readable medium to generate substantially linear, analog control signals to adjust amplitude contributions of phases of a reference clock signal to facilitate interpolation of a changing phase of an interpolated clock signal with substantially analog transitions.

Abstract: Apparatus, systems and methods for CMOS image sensor array optimization for both bright and low light applications are disclosed. In one implementation, an apparatus includes an imaging array, the array including at least pixels of a first type having a first charge storage capacity and pixels of a second type having a second charge storage capacity. Other implementations are disclosed.

Abstract: A method that measures a skew between a data signal and a clock signal at a receiving end of a serial link and then adjusts a phase relationship between the data signal and the clock signal to reduce the skew.

Abstract: An arrangement for generating a clock signal. Embodiments provide a method, apparatus, system, and machine-readable medium to interpolate phases of a reference clock signal to output an interpolated clock signal. Some embodiments may output the clock signal as a recovered clock signal for a phase interpolator-based clock recovery system. Many embodiments may interpolate a changing phase of an interpolated clock signal with substantially analog transitions.

Abstract: An arrangement for a phase interpolator based clock recovery system, a phase interpolator, and a voltage controller for a highly linear phase interpolator system is provided. Embodiments comprise a method, apparatus, system, and machine-readable medium to recover a clock signal for clocked data based on a local clock signal. In some embodiments, the local clock signal may also be used to transmit the clocked data.

Abstract: A method is described that includes sampling data at a plurality of different relative phase positions between a clock signal and a data signal. The method also includes separately adjusting both the data signal's phase position and the clock signal's phase position to change the relative phase positions between the clock signal and the data signal at which data is sampled. Circuitry capable of performing the method is also described.

Abstract: Some embodiments provide a plurality of capacitors coupled in parallel and a plurality of capacitor switches, each one of the capacitor switches coupled in series with a respective one of the plurality of capacitors. Also provided may be a plurality of control circuits, each of the plurality of control circuits coupled to a respective one of the plurality of capacitor switches, to generate a respective control voltage, and to independently set a respective one of the plurality of capacitor switches to the respective control voltage, and a plurality of control switches, each of the plurality of control switches to couple and to decouple a respective one of the plurality of control circuits to and from a control signal.

Abstract: Some embodiments provide a switch capacitor circuit to generate a first output capacitance based on a control signal, a main loop circuit to generate an output signal based on the control signal, and an oscillating circuit to generate an oscillating signal, a frequency of the oscillating signal based at least on the first output capacitance and the output signal.

Abstract: Some embodiments provide a charge pump to output a first control signal and a second control signal based on a frequency of an oscillating signal and a reference frequency, a switch capacitor circuit to generate a first output capacitance based on the first control signal, a main loop circuit to generate an output signal based on the second control signal, and an oscillating circuit to generate the oscillating signal, the frequency of the oscillating signal based at least on the first output capacitance and the output signal.

Abstract: Some embodiments provide a plurality of capacitors coupled in parallel, a plurality of capacitor switches, each one of the capacitor switches coupled in series with a respective one of the plurality of capacitors, one or more biasing circuits to independently set each of the plurality of capacitor switches to one of a reset voltage, a first threshold voltage, and a second threshold voltage, and a plurality of control switches, each of the control switches to couple and to decouple a respective one of the plurality of capacitor switches to and from a control voltage.

Abstract: Some embodiments provide a plurality of capacitors coupled in parallel and a plurality of capacitor switches, each one of the capacitor switches coupled in series with a respective one of the plurality of capacitors. Also provided may be a plurality of control circuits, each of the plurality of control circuits coupled to a respective one of the plurality of capacitor switches, to generate a respective control voltage, and to independently set a respective one of the plurality of capacitor switches to the respective control voltage, and a plurality of control switches, each of the plurality of control switches to couple and to decouple a respective one of the plurality of control circuits to and from a control signal.

Abstract: Some embodiments provide a plurality of capacitors coupled in parallel, a plurality of capacitor switches, each one of the capacitor switches coupled in series with a respective one of the plurality of capacitors, one or more biasing circuits to independently set each of the plurality of capacitor switches to one of a reset voltage, a first threshold voltage, and a second threshold voltage, and a plurality of control switches, each of the control switches to couple and to decouple a respective one of the plurality of capacitor switches to and from a control voltage.

Abstract: A method is described that involves directing a signal through a hysteresis comparator. Then, determining if an output signal of the hysteresis comparator, in response to the signal, is an AC signal or a DC signal. Then, deactivating a signal reception unit that receives the signal if the hysteresis comparator output signal corresponds to a DC signal; or, activating the signal reception unit if the hysteresis comparator output signal corresponds to an AC signal.