Abstract: A self correcting single event upset-hardened CMOS register comprises a master portion and a slave portion. The master portion is coupled to a source of data and includes a feedback means such that said master portion can store said data during the first phase of a bi-phase clock signal. A slave portion including a second feedback path, has an input coupled to the output of said master portion and has an output which comprises the output of the register. An odd plurality of inverters is placed in series in the feedback path so as to isolate each node which is a possible site for high-energy particle impingement from other nodes in the loop and to attenuate and delay any resulting impulses such that the state of the error pulse cannot be maintained thus permitting the slave loop to remain in the state determined by the preceding data pulse.

Abstract: A voltage translator circuit is provided to reduce a supply voltage to a lower, predetermined, relatively constant and unconditionally stable operating voltage without the use of external components. A voltage divider comprising a plurality of series connected CMOS FETs located in P-regions, is used to establish an operating voltage. Additional CMOS FETs are used to supply the load current and control the no-load voltage.

Abstract: An integrated circuit and method includes a substrate bias voltage control circuit formed on a common substrate therewith for ensuring that the substrate has a voltage applied thereto while a semiconductor device on the substrate has a supply voltage applied thereto which includes means for providing sources of bias and supply voltages to the substrate with means for firstly coupling the bias voltage to the substrate when the bias voltage is present and means for secondly coupling the supply voltage to the substrate when the bias voltage is not present.

Abstract: A method and an apparatus are disclosed for converting an analog input signal having either a positive or negative polarity into a digital output signal indicating the magnitude and polarity of the input signal. Amplifier offset voltages and dynamic hysteresis in the comparator are compensated automatically and a zero reference is established automatically to provide a corrected output. A compensation capacitor and an integrating capacitor are selectively charged. A reference signal is integrated to measure the magnitude of the difference between the integrator offset voltage and the comparator threshold. A digital representation of the time required to measure the difference between the integrator offset voltage and the comparator threshold is stored. The compensation capacitor and the integrating capacitor are again selectively charged. The analog input signal is then integrated for a fixed time. The reference signal is integrated for a time equivalent to the digitally stored time.