Abstract: A toroidal interconnect structure is continuous, symmetrical, and non-breaking for the connection of logic and other resources in a semiconductor or other device. The toroidal interconnect structure allows logical and electrical components that physically are implemented in two-dimensional silicon to be organized and connected in a continuous, homogeneous, symmetrical and non-breaking three-dimensional fashion. Instead of connecting components to their nearest neighbors, the connections in the toroidal interconnect skip adjacent rows and columns of interior components and connect directly to components that are physically two rows or columns away. By continuing to skip rows or columns across the device and eventually looping back and connecting the remaining “skipped” components, the continuous, non-breaking connection path is created.

Abstract: A self-configuring processing element for providing arbitrarily wide, application-specific instruction set extensions to an Instruction Set Architecture (ISA) microcontroller includes a System Bus Interface and Instruction Handler (SBI), an Input Router and Conditioner (IRC), an ALU, a Memory, and an Output Router. The SBI may accept address, data and control signals and may include a unique address decoder, an instruction register that decodes address and data bits, a state machine for sequencing through initialization and instruction set-up, and transceivers for controlling data flow with the system bus and feedback. The IRC may select information to transmit to the ALU and/or the Memory and may include circuitry for registering, shifting, incrementing, and decrementing inputted information. The ALU and the Memory may perform operations on the output of the IRC. The Output Router may route the output of the ALU and/or the Memory to one or more possible destinations.

Abstract: A reconfigurable processor for processing digital logic functions includes a microcontroller, one or more decoders connected to the microcontroller, a plurality of interconnection busses; and a plurality of processing elements is described. Each processing element connects to one or more other processing elements by local interconnection paths and to a decoder. The plurality of processing elements are arranged in one or more pipeline stages each including one or more processing elements. A method of dynamically reconfiguring a pipelined processor including configuring, using a microcontroller, a plurality of pipeline stages each including one or more processing elements, processing data through one or more pipeline stages, reconfiguring, by the microcontroller, one or more pipeline stages to define one or more subsequent pipeline stages, and routing the processed data through the one or more reconfigured pipeline stages is also described.

Abstract: Input interfaces convert a predetermined data frame structure, such as a Sonet STS-1, into an internal format comprising a predetermined number of rows and columns, the rows being a multiple of a number evenly divisible into the bytes contained in the internal frame format. A time-space switch switches the frame format while storing a row of bytes in a data memory. Output interfaces convert the switched data to the same type of data frame format received at the input.

Abstract: A cart for collection and safe disposal of low level radioactive wastes (LLRW) comprised of a compartment which is shielded to protect against exposure to radioactivity. The unique construction of the cart includes a sandwich construction of the compartment walls and ceiling wherein a thin layer of lead is sandwiched between coextensively bonded layers of methyl methacrylate polymer (Lucite).