Abstract: A GPIB system for capturing GPIB signals at a predetermined rate and upon valid transitions of the data valid signal. A first sampling circuit samples the GPIB at the predetermined rate and a second sampling circuit samples the GPIB with transitions of the data valid signal. Capture logic preferably includes data valid logic for monitoring the data valid signal to assure valid transitions. The capture logic also preferably includes select logic for selecting between the GPIB signals sampled at the predetermined rate and upon assertion of the data valid signal, where data valid signal transitions preferably have higher priority. The capture logic monitors the sampled GPIB signals and the data valid logic to enable a first-in, first-out buffer to capture sampled data upon predetermined capture conditions and upon transitions of the data valid signal. In this manner, data signal transitions which might otherwise be missed by the predetermined sampling rate are sampled and captured.

Abstract: A deglitch circuit for filtering false transitions of an input signal based on transitions of a clock signal. A plurality of memory devices as provided for detecting the input signal being assay for two, three and five transitions of the clock signal in the preferred embodiment. Programmable select logic is also provided for selecting between these three cases. In the preferred embodiment, six separate flip-flops are included and clocked by the clocked signal, four of the flip-flops being reset upon spurious negations of the input signal for reign such transitions, and where two of the four flip-flops are clocked on the rising edge whereas the other two are clocked on the falling edge of the clock signal. The programmable select logic preferably includes a multiplexer for choosing between the three cases. In the preferred embodiment, the input signal is the data valid (DAV) signal of a GPIB, where the deglitch circuit assures valid data sampling on a GPIB.

Abstract: A time-stamp timer for a GPIB system including a counter for providing elapsed time values and capture logic for capturing GPIB samples upon predetermined conditions and for capturing a maximum elapsed time value upon rollover of the counter. The GPIB samples and time values are preferably captured into a first-in, first-out (FIFO) buffer. The capture logic preferably resets the counter after GPIB signals are captured due to the predetermined conditions, so that each time value represents an elapsed time between GPIB samples. If the counter reaches a rollover condition, the capture logic causes another capture into the buffer for capturing the maximum elapsed time value. Thus, any consecutive maximum elapsed time values are summed with a final elapsed time value to determine elapsed time between any two valid GPIB captures. In one embodiment, marker logic marks each first occurrence of the maximum elapsed time value to notify software of timer rollover.

Abstract: A GPIB circuit card including a GPIB controller and GPIB analyzer on the same circuit card. The combined controller and analyzer allows a single connection to the GPIB and only uses a single I/O slot of a host computer. Bus interface circuitry on the card allows both the controller and analyzer to communicate to the host computer using the same bus connector. The GPIB controller preferably operates independently of and concurrently with the GPIB analyzer. Thus, a GPIB circuit card according to the present invention conserves computer resources.

Abstract: A GPIB system including a parallel poll detection system for capturing signals of a GPIB in response to a parallel poll command. Capture logic includes sampling circuitry for continually sampling the GPIB signals, where the capture logic further stores the samples into a buffer upon desired conditions. A parallel poll detection circuit detects a parallel poll command asserted and subsequently negated on the GPIB, and correspondingly causes GPIB samples to be captured on both of these events. Also, a timer circuit causes the GPIB signals to be captured a predeteremined time period after the assertion of each parallel poll command. In the preferred embodiment, transition detect logic further causes GPIB samples to be captured if any transition of GPIB data signals occur while the parallel poll command is asserted on the GPIB.

Abstract: Disclosed are a configuration-dependent video memory clock selection circuit and method for a computer system. The selection circuit operates in conjunction with a removable video memory module. The module comprises: (1) a circuit board capable of insertion into the computer system as a daughter-card, (2) a plurality of video memory chips located on the circuit board and having a particular logical configuration and (3) a configuration indication circuit located on the circuit board, the indication circuit capable of providing a configuration signal representing the particular logical configuration to video clock signal generator circuitry in the computer system when the circuit board is inserted into the computer system. Thus, the configuration indication circuit and the video clock signal generator circuitry act in concert to provide a configuration-dependent video memory clock selection circuit.