Abstract: An apparatus includes an input interface circuit and a processing circuit. The input interface circuit may be configured to receive a high dynamic range (HDR) image data stream. The HDR image data stream generally comprises a plurality of HDR image frames comprising a plurality of exposure regions having different exposure levels. The processing circuit may be configured to store image data for the plurality of HDR image frames in a memory. The processing circuit generally issues write commands to store the image data of all of the exposure regions for a particular HDR image frame in one of a plurality of memory buffers in the memory. The processing circuit generally issues row increment commands during one or both of blanking periods and sensor overlap regions of the HDR image frames based upon symbols in the HDR image data stream.

Abstract: An apparatus includes a scheduler circuit and a processing circuit. The scheduler circuit may be configured to (i) parse a directed acyclic graph into one or more operators and (ii) schedule the one or more operators in one or more data paths. The processing circuit generally comprises one or more hardware engines configured as the one or more data paths. The one or more hardware engines are generally configured to generate one or more output vectors in response to zero or more input vectors using the operators. At least one of the one or more hardware engines may support input vector dimensions ranging from zero to at least four dimensions. At least one of the one or more hardware engines is implemented solely in hardware.

Abstract: An apparatus includes a memory and a processor. The memory may be configured to store a directed acyclic graph. The processor may be configured to (i) receive a command to run the directed acyclic graph, (ii) parse the directed acyclic graph into a data flow including one or more operators, (iii) schedule the operators in one or more data paths, and (iv) generate one or more output vectors by processing one or more input vectors in the data paths. The processor generally comprises a plurality of hardware engines. The data paths may be implemented with the hardware engines. The hardware engines may operate in parallel to each other.

Abstract: An apparatus includes a memory and a processor. The memory generally comprises a first memory buffer and a second memory buffer. The first and the second memory buffers may be independent of each other. The processor may be configured to store image data for a plurality of image frames in the memory. Each frame generally comprises a plurality of exposure regions having different exposure levels. The processor stores image data of all of the exposure regions for a particular image frame in one of the memory buffers along with respective overlap regions. The overlap regions are generated by the processor performing a row increment operation based upon symbols in an image data stream.

Abstract: An apparatus includes a scheduler circuit and a plurality of hardware engines. The scheduler circuit may be configured to (i) store a directed acyclic graph, (ii) parse the directed acyclic graph into a plurality of operators and (iii) schedule the operators in one or more data paths based on a readiness of the operators to be processed. The hardware engines may be (i) configured as a plurality of the data paths and (ii) configured to generate one or more output vectors by processing zero or more input vectors using the operators.

Abstract: An apparatus includes a scheduler circuit and a plurality of hardware engines. The scheduler circuit may be configured to (i) store a directed acyclic graph, (ii) parse the directed acyclic graph into a plurality of operators and (iii) schedule the operators in one or more data paths based on a readiness of the operators to be processed. The hardware engines may be (i) configured as a plurality of the data paths and (ii) configured to generate one or more output vectors by processing zero or more input vectors using the operators.

Abstract: An apparatus includes a scheduler circuit and a plurality of hardware engines. The scheduler circuit may be configured to (i) store a directed acyclic graph, (ii) parse the directed acyclic graph into one or more operators and (iii) schedule the one or more operators in one or more data paths. The hardware engines may be (i) configured as a plurality of the data paths and (ii) configured to generate one or more output vectors by processing zero or more input vectors using the operators. One or more of the hardware engines supports a range of multiple dimensions of the input vectors from zero dimensions to at least four dimensions.

Abstract: An apparatus includes a processor and a coprocessor. The processor may be configured to generate a command to run a directed acyclic graph. The coprocessor may be configured to (i) receive the command from the processor, (ii) parse the directed acyclic graph into a data flow including one or more operators, (iii) schedule the operators in one or more data paths and (iv) generate one or more output vectors by processing one or more input vectors in the data paths. The data paths may be implemented with a plurality of hardware engines. The hardware engines may operate in parallel to each other. The coprocessor may be implemented solely in hardware.

Abstract: An apparatus includes an arbiter circuit and a translation circuit. The arbiter circuit may be configured to generate a first address signal in a virtual memory space by arbitrating among a plurality of clients to access a physical memory space. The clients may be classified as either privileged clients or non-privileged clients. The physical memory space may comprise at least one secure space. The translation circuit may be configured to generate a second address signal by translating a page in the virtual memory space into the physical memory space based on the first address signal. The page may corresponds to a particular one of the clients that won the arbitration. The page may be translated (a) into the secure space if the particular client is one of the privileged clients and (b) outside the secure space otherwise.

Abstract: An arbiter circuit and a translation circuit. The arbiter circuit may be configured to generate a first address signal in a virtual memory space by arbitrating among a plurality of clients to access a physical memory space. The clients may be classified as either privileged clients or non-privileged clients. The physical memory space may comprise at least one secure space. The secure space may be used to protect data of the privileged clients from being accessed by the non-privileged clients. The translation circuit may be configured to generate a second address signal by translating a page in the virtual memory space into the physical memory space. The page may correspond to a particular one of the clients that won the arbitration. The page may translate into the secure space if the particular client is one of the privileged clients. The page may also translate outside the secure space if the particular client is one of the non-privileged clients.

Abstract: An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.

Abstract: An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.

Abstract: An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.

Abstract: The present invention is a method and apparatus for compiler optimization that determines the maximum number of live computer registers, or pressure point. The present invention improves the productivity of a software developer by reducing compilation time of a computer program. More particularly, the overhead required during compilation to search information to determine the maximum number of live registers is reduced. The present invention records the relevant events related to the execution of a computer program, as opposed to a comprehensive history of the read instructions and write instructions. Also, the present invention maintains information about the maximum number of live registers for any partition related to the execution of a computer program. The present invention may bound the required system resources required to determine the maximum number of live registers to the number of registers associated with the number of partitions.

Abstract: The present invention is a method and apparatus for compiler optimization that determines the maximum number of live computer registers, or pressure point. The present invention improves the productivity of a software developer by reducing compilation time of a computer program. More particularly, the overhead required during compilation to search information to determine the maximum number of live registers is reduced.

Abstract: The present invention is a method and apparatus for compiler optimization that determines the maximum number of live computer registers, or pressure point. The present invention improves the productivity of a software developer by reducing compilation time of a computer program. More particularly, the overhead required during compilation to search information to determine the maximum number of live registers is reduced. The present invention records the relevant events related to the execution of a computer program, as opposed to a comprehensive history of the read instructions and write instructions. Also, the present invention maintains information about the maximum number of live registers for any partition related to the execution of a computer program. The present invention may bound the required system resources required to determine the maximum number of live registers to the number of registers associated with the number of partitions.