Abstract: A reconfigurable computing system and method of use are provided for interfacing a plurality of application programs running on a host system to one or more hardware objects defined in one or more configuration files. The system includes reconfigurable computing circuitry comprising flexibly configurable circuitry operable for interfacing and implementing one or more hardware objects with one or more of the application programs. The system further includes memory circuitry associated with the reconfigurable computing circuitry for system information storage, and communications interfaces for connecting the reconfigurable computing circuitry and the memory to the host computer. The flexibly configurable circuitry further comprises one or more FPGAs and one or more programmable logic devices (“PLDs”), SRAM and EEPROM memory, and all the necessary connectors and support circuitry.

Abstract: A system and method of private, three-key data encryption, secure storage, secure transmission and decryption is disclosed. The system is comprised of three core components, including a data server, a user device and a security server. The data server and user device have private security keys associated therewith. A third key is generated at the security server. The third key is transmitted to the data server and user device in encrypted form, using the data server security key to encrypt the third key as it is transmitted to the data server, and the user device security key to encrypt the third key as it is transmitted to the user device. As a result, a secure data transmission session may be established.

Abstract: An asynchronous digital mixer (20) receives digitally sampled audio signal data at different unrelated asynchronous sampling rates. The audio data is then edge synchronized and mixed using a summing element (28) and an oversampled sigma delta digital modulator (42), where a single bit output of the digital modulator (42) can be output as an analog signal with the use of a smoothing filter (46), or further decimated using a digital decimation filter (44) for storage on a digital media. Additionally, analog audio signals can be converted and mixed digitally within the system using an analog interface (35) without having to decimate and filter each analog input signal individually.

Abstract: A method and apparatus for extracting digital information (111) from an asynchronous data stream (101) is achieved by providing a data stream (101) that is clocked at a data stream clock rate (210). A sampled data stream (103) is produced by sampling the asynchronous data stream at a first clock rate (105), which is independent of the data stream clock rate (210). Using the sampled data stream (103), a recovered clock (107) is generated. The recovered clock (107) is then used to extract the digital information (111) from the sampled data stream (103).

Abstract: A sigma-delta modulator (50, 100) attenuates a frequency domain characteristic of a feedback signal to a first stage (60) of the modulator (50, 100) near f.sub.s /2, where f.sub.s is the modulator's (50, 100) clock frequency. The modulator (50, 100) thus virtually eliminates in-band tones which are characteristic of known sigma-delta modulators, without complex dithering schemes. In one embodiment, the sigma-delta modulator (50, 100) includes a two-tap finite impulse response (FIR) filter (80) within a feedback loop of the modulator (50, 100). The two-tap FIR filter (80) smoothes transitions at an output of a second stage (70) to provide the feedback signal to the first stage (60). This architecture is useful for either a digital-to-analog sigma-delta modulator (50) or an analog-to-digital sigma-delta modulator (100).

Abstract: A flexible data interface (21, 22) for a digital-to-analog converter (25, 26) includes a mute circuit (46, 70, 71 ) to mute and de-mute input data in 6 dB steps over a time period such as one-quarter of a second. The mute circuit includes a counter (46) to provide mute signals, a decoder (70) to decode the mute signals, and a shift matrix (71) to shift the data from zero to the maximum number of bits in response to the decoded signals. The interface (21, 22) includes a programmable shift register (43) to allow different data word lengths, such as 20-, 18-, or 16-bit, to be presented to the digital-to-analog converter (25, 26). The interface (21, 22) also includes a multiplexer (47) to allow left- and right-channel data to be received either time-multiplexed on a single pin, or on two separate pins.

Abstract: A sigma-delta digital-to-analog converter (DAC) (40) receives oversampled input data representative of an analog signal. The data may be optionally interpolated to a higher rate in a interpolator (41). A noise-shaping sigma-delta modulator (42) is connected to the output of the interpolator (41). The output of the modulator (42) is provided to a finite impulse response (FIR) filter (43). The FIR filter (43) has a frequency response characteristic which reduces the shaped noise and aliased components. This noise has a tendency to intermodulate back into the DAC's passband. The FIR filter (43) uses a series of flip-flops (81, 82, 83) functioning as delay elements with well-controlled timing edges. The outputs of the flip-flops (81, 82, 83) control current sources (91, 92, 93) weighted according to corresponding filter coefficients. The outputs of the current sources (91, 92, 93) are then summed in a summing device such as an amplifier (101).

Abstract: A digital-to-analog converter (20) includes a linear interpolator (24) and a converter (25, 26) such as a sigma-delta modulator (25) and an associated analog summing network (26). The linear interpolator (24) includes a differentiator (200), an integrator (202), and a multiplexer (201). The differentiator (200) differentiates a received signal at a first rate. The multiplexer (201) multiplexes an output of the differentiator (200) to provide a multiplexed signal having a larger number of bits than the received signal in order to support multiple interpolating ratios. The integrator (202) integrates the multiplexed signal at a second rate to present to the converter (25, 26). By connecting the multiplexer (201) between the differentiator (200) and the integrator (202), the digital-to-analog converter (20) minimizes the size of the linear interpolator (24) while relieving a critical path between the linear interpolator (24) and the converter (25, 26).

Abstract: A sigma-delta digital-to-analog converter (20) reduces even order distortion, such as a DC offset, in an output signal by chopping the output signal alternately with set and reset pulses. The sigma-delta digital-to-analog converter (20) includes a sigma-delta modulator (25), a chop circuit (261) associated with a corresponding bit of the sigma-delta modulator (25), and an output buffer (264) for providing the output signal. The chop circuit (261) alternately inserts first and second logic levels into an output data stream of the sigma-delta modulator (25) before providing it to the output buffer (264). Even-order distortion is eliminated with only a tolerable attenuation of the output signal.

Abstract: A digital-to-analog converter (20) with improved performance includes an offset/scaler (23), a sigma-delta modulator (25), and an analog summing network (26). In one embodiment, the offset/scaler (23) scales an input signal by a predetermined amount, such as three-quarters, to compensate for nonlinearities in a transfer characteristic of the sigma-delta modulator (25). In another embodiment, the sigma-delta modulator (25) is a sufficiently-resolved sigma-delta modulator. The offset/scaler (23) provides an offset to the sufficiently-resolved sigma-delta modulator (25) sufficient to force a coarse bit thereof into an idle pattern.

Abstract: A digital signal having a plurality of bits is apportioned by the DAC into a plurality of words, at least one of which has a plurality of bits. Each of the plurality of words is then processed in an energy signal producing means, such as a .SIGMA.-.DELTA. modulator, to produce an output energy signal whose time average represents the input digital word portion. The energy output signals are then summed to provide the analog signal.

Abstract: A digital signal having a plurality of bits is received by a converter. Two of the bits, the most significant bit and a second bit which is not the most significant bit or the second most significant bit, are tapped from the output and used as a feedback signal. These two bits are also used to form an analog output signal. The two bits are attenuated using a weighted network and then summed to provide the analog output signal.

Abstract: An analog signal is input to a converter where a feedback signal is subtracted to form an analog error signal. The analog error signal is then processed through a first quantizer to provide a course output bit. The difference between the input and output of the first quantizer is then processed through a second quantizer to provide a trim output bit. The two bits are combined and returned as the feedback signal and are provided to a decimation filter which will provide the digital output representation of the analog input.

Abstract: An integrated circuit which contains an on-chip clock that operates the integrated circuit at its true maximum speed is disclosed. The integrated circuit operates asynchronously from a processor bus and contains circuitry for interfacing with the processor bus. A clock generator is constructed using information obtained from identifying a slowest signal path of the integrated circuit. The clock may be stopped and started under processor control to permit communication between the IC and processor bus.