Abstract: A test structure includes an active region formed in a semiconducting substrate, a first line formed above and extending over an upper surface of the active region, and a first isolation region formed in the semiconducting substrate, wherein the active region surrounds the first isolation region. The test structure further includes a first extension formed above the active region and on and in contact with an upper surface of the first isolation region, wherein the first extension extends laterally over the upper surface of the active region from a first side of the first line. Additionally, the first line and the first extension are comprised of at least one of a high-k layer of insulating material and a metal layer.

Abstract: One example of a method disclosed herein for forming a gate electrode in a field effect transistor comprises forming a gate structure above a semiconductor substrate, the gate structure comprising a gate electrode and a gate cap layer positioned above the gate electrode, forming sidewall spacers adjacent the sidewalls of the gate structure, forming a semiconductor layer above portions of the source/drain regions not covered by the gate structure and the sidewall spacers and performing at least one etching process to remove the gate cap layer from above the gate electrode and to remove at least a portion of the semiconductor layer.

Abstract: A test structure includes an active region formed in a semiconducting substrate, a first line formed above and extending over an upper surface of the active region, and a first isolation region formed in the semiconducting substrate, wherein the active region surrounds the first isolation region. The test structure further includes a first extension formed above the active region and on and in contact with an upper surface of the first isolation region, wherein the first extension extends laterally over the upper surface of the active region from a first side of the first line. Additionally, the first line and the first extension are comprised of at least one of a high-k layer of insulating material and a metal layer.

Abstract: Disclosed herein are various electrical test structures for evaluating semiconductor devices that employ high-k dielectrics and/or metal gate electrode structures. In one example, the test structure disclosed herein includes a first line formed over an isolation material, a first active region defined in a semiconducting substrate and a first extension formed over an isolation material, the first extension extending from a first side of the first line, wherein the first extension is positioned proximate the first active region and wherein the first line and the first extension are comprised of at least one of a high-k layer of insulating material or a metal layer.

Abstract: One example of a method disclosed herein for forming a transistor surrounded by an isolation structure includes the steps of, prior to forming the isolation structure, forming a semiconductor material on a region of a semiconducting substrate, after forming the semiconductor material, forming the isolation structure in the substrate around the semiconductor material, and forming a gate structure above the semiconductor material.

Abstract: One example of a method disclosed herein for forming a transistor surrounded by an isolation structure includes the steps of, prior to forming the isolation structure, forming a semiconductor material on a region of a semiconducting substrate, after forming the semiconductor material, forming the isolation structure in the substrate around the semiconductor material, and forming a gate structure above the semiconductor material.

Abstract: One illustrative method disclosed herein includes forming a layer of insulating material above a surface of a semiconducting substrate, performing a first etching process on the layer of insulating material to define a plurality of trenches in the layer of insulating material, wherein each of the trenches exposes a portion of the surface of the substrate, performing an epitaxial growth process to form a fin comprised of a semiconductor material in each of the trenches, and, after forming the fins, performing a second etching process on the layer of insulating material to thereby reduce a thickness of the layer of insulating material and thereby define a local isolation region positioned between the plurality of fins.

Abstract: Disclosed herein are various electrical test structures for evaluating semiconductor devices that employ high-k dielectrics and/or metal gate electrode structures. In one example, the test structure disclosed herein includes a first resistor comprised of at least one of a high-k layer of insulating material or a metal layer and a silicon-containing material layer and first and second spaced-apart metal silicide regions formed on the silicon-containing material layer, wherein the silicon-containing layer further comprises a non-silicided region positioned between the first and second spaced-apart metal silicide regions.

Abstract: Disclosed herein are various electrical test structures for evaluating semiconductor devices that employ high-k dielectrics and/or metal gate electrode structures. In one example, the test structure disclosed herein includes a first line formed over an isolation material, a first active region defined in a semiconducting substrate and a first extension formed over an isolation material, the first extension extending from a first side of the first line, wherein the first extension is positioned proximate the first active region and wherein the first line and the first extension are comprised of at least one of a high-k layer of insulating material or a metal layer.

Abstract: In one embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and a secondary signal path including a pulse shaping stage incorporating a network and a scaling stage. The pre-emphasis circuit generates an overshoot pulse with variable pulse width. In another embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and one or more secondary signal paths incorporating a network implementing a specific transient response. Each of the secondary signal paths includes a scaling stage and a shaping stage each with programmable bias current. The scaling stage can be configured before or after the shaping amplifier. The pre-emphasis circuit generates an overshoot signal with variable amplitude and/or variable width.

Abstract: In one embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and a secondary signal path including a pulse shaping stage incorporating a network and a scaling stage. The pre-emphasis circuit generates an overshoot pulse with variable pulse width. In another embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and one or more secondary signal paths incorporating a network implementing a specific transient response. Each of the secondary signal paths includes a scaling stage and a shaping stage each with programmable bias current. The scaling stage can be configured before or after the shaping amplifier. The pre-emphasis circuit generates an overshoot signal with variable amplitude and/or variable width.

Abstract: A transmission line pre-emphasis circuit includes a primary signal path receiving a digital data stream and generating a primary output current indicative of the digital data stream, one or more secondary signal paths each incorporating a network implementing a specific transient response where the one or more secondary signal paths receive the digital data stream and generate secondary output currents representing one or more overshoot signals indicative of the transient response of the respective network. The one or more secondary signal paths have variable gain being programmed through respective DC programming signals. The secondary output currents are summed with the primary output current. The transmission line pre-emphasis circuit further includes an output loading stage coupled to generate from the summed current a pre-emphasized digital output signal indicative of the one or more overshoot signals added to the digital data stream.

Abstract: A transmission line equalizer includes multiple signal paths connected in parallel between an equalizer input signal and an output amplifier where each signal path has a network implementing a specific frequency dependent response and each signal path implements current gain amplification with one or more of the signal paths having a variable gain programmed through a time invariant, DC programming signal. Furthermore, one or more of the signal paths implements linear-to-nonlinear signal transformations and compensating nonlinear-to-linear signal transformations to generate linearized output signals at the one or more signal paths. The equalizer further includes the output amplifier summing output signals from the multiple signal paths to generate an equalized output signal. In operation, the gain of the one or more signal paths is varied to establish the relative proportions of the output signals generated by each signal path and summed at the output amplifier.

Abstract: In one embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and a secondary signal path including a pulse shaping stage incorporating a network and a scaling stage. The pre-emphasis circuit generates an overshoot pulse with variable pulse width. In another embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and one or more secondary signal paths incorporating a network implementing a specific transient response. Each of the secondary signal paths includes a scaling stage and a shaping stage each with programmable bias current. The scaling stage can be configured before or after the shaping amplifier. The pre-emphasis circuit generates an overshoot signal with variable amplitude and/or variable width.

Abstract: A transmission line pre-emphasis circuit includes a primary signal path receiving a digital data stream and generating a primary output current indicative of the digital data stream, one or more secondary signal paths each incorporating a network implementing a specific transient response where the one or more secondary signal paths receive the digital data stream and generate secondary output currents representing one or more overshoot signals indicative of the transient response of the respective network. The one or more secondary signal paths have variable gain being programmed through respective DC programming signals. The secondary output currents are summed with the primary output current. The transmission line pre-emphasis circuit further includes an output loading stage coupled to generate from the summed current a pre-emphasized digital output signal indicative of the one or more overshoot signals added to the digital data stream.

Abstract: A transmission line equalizer includes multiple signal paths connected in parallel between an equalizer input signal and an output amplifier where each signal path has a network implementing a specific frequency dependent response and each signal path implements current gain amplification with one or more of the signal paths having a variable gain programmed through a time invariant, DC programming signal. Furthermore, one or more of the signal paths implements linear-to-nonlinear signal transformations and compensating nonlinear-to-linear signal transformations to generate linearized output signals at the one or more signal paths. The equalizer further includes the output amplifier summing output signals from the multiple signal paths to generate an equalized output signal. In operation, the gain of the one or more signal paths is varied to establish the relative proportions of the output signals generated by each signal path and summed at the output amplifier.

Abstract: In one embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and a secondary signal path including a pulse shaping stage incorporating a network and a scaling stage. The pre-emphasis circuit generates an overshoot pulse with variable pulse width. In another embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and one or more secondary signal paths incorporating a network implementing a specific transient response. Each of the secondary signal paths includes a scaling stage and a shaping stage each with programmable bias current. The scaling stage can be configured before or after the shaping amplifier. The pre-emphasis circuit generates an overshoot signal with variable amplitude and/or variable width.

Abstract: A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of opposite conductivity types. The first region of the diode and the third region of the programmable structure are electrically connected. In operation, the programmable structure is programmed to a low impedance state when a voltage exceeding a first breakdown voltage of the programmable structure is applied to reverse bias the programmable structure. The programmable element can be used to form a programmable array having very low parasitic capacitance, enabling the realization of a large and ultra fast programmable logic array.

Abstract: A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of opposite conductivity types. The first region of the diode and the third region of the programmable structure are electrically connected. In operation, the programmable structure is programmed to a low impedance state when a voltage exceeding a first breakdown voltage of the programmable structure is applied to reverse bias the programmable structure. The programmable element can be used to form a programmable array having very low parasitic capacitance, enabling the realization of a large and ultra fast programmable logic array.

Abstract: A semiconductor-wafer chuck for heating and cooling a device-under-test includes a heat-spreader plate with a clamping surface for a semiconductor wafer. A heater is disposed within the heat-spreader plate. A chiller heat-exchanger provides for heat removal. A motion control system is used to move the chiller heat-exchanger in relation to the heat-spreader plate, and thus provide for an adjustment of the thermal resistance and thermal coupling between the two. The heater comprises electric heating elements with a variable power input, and the chiller heat-exchanger is moved sufficiently far away to prevent boiling and evaporation of a coolant disposed inside. A device-under-test temperature controller controls the device-under-test temperature by adjusting the heater power, chiller fluid temperature and/or by moving the chiller heat-exchanger in relation to the heat spreader plate.