Patents by Inventor Robert C. Marrs

Robert C. Marrs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6163463
    Abstract: An interconnection between bonding pads on an integrated circuit chip and corresponding bonding contacts on a substrate are formed. To form the interconnection, a metallization is formed on each of the substrate bonding contacts. Metal ball bond bumps are formed on selective ones of the bonding pads and then coined. The substrate and integrated circuit chip are heated. The coined ball bond bumps are then placed into contact with the corresponding metallizations, pressure and ultrasonic energy are applied, and a metal-to-metal bond is formed between each coined ball bond bump and the corresponding metallization.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: December 19, 2000
    Assignee: Amkor Technology, Inc.
    Inventor: Robert C. Marrs
  • Patent number: 5795818
    Abstract: An interconnection between bonding pads on an integrated circuit chip and corresponding bonding contacts on a substrate are formed. To form the interconnection, a metallization is formed on each of the substrate bonding contacts. Metal ball bond bumps are formed on selective ones of the bonding pads and then coined. The substrate and integrated circuit chip are heated. The coined ball bond bumps are then placed into contact with the corresponding metallizations, pressure and ultrasonic energy are applied, and a metal-to-metal bond is formed between each coined ball bond bump and the corresponding metallization.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: August 18, 1998
    Assignee: Amkor Technology, Inc.
    Inventor: Robert C. Marrs
  • Patent number: 5722161
    Abstract: A packaged semiconductor die includes a heat sink having a locking feature that interlocks with the encapsulant encapsulating the die to minimize or eliminate delamination of the encapsulant from the heat sink. A surface of the heat sink can be exposed to the exterior of the encapsulant. The invention applies broadly to packaged integrated circuits including multichip modules and hybrid circuits, as well as to packaged transistors. In one embodiment of the invention, a locking moat has a cross-sectional shape that has, at a first distance beneath a locking surface of the heat sink, a width that is larger than a width at a second distance beneath the locking surface, the second distance being smaller than the first distance. The locking moat can have, for example, a "keyhole" cross-sectional shape or a circular cross-sectional shape. The locking moat can be formed by, for example, stamping or chemical etching. In another embodiment of the invention, the locking feature is a locking region.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: March 3, 1998
    Assignee: Amkor Electronics, Inc.
    Inventor: Robert C. Marrs
  • Patent number: 5701034
    Abstract: A packaged semiconductor die includes a heat sink having a locking feature that interlocks with the encapsulant encapsulating the die to minimize or eliminate delamination of the encapsulant from the heat sink. A surface of the heat sink can be exposed to the exterior of the encapsulant. The invention applies broadly to packaged integrated circuits including multichip modules and hybrid circuits, as well as to packaged transistors. In one embodiment of the invention, a locking moat has a cross-sectional shape that has, at a first distance beneath a locking surface of the heat sink, a width that is larger than a width at a second distance beneath the locking surface, the second distance being smaller than the first distance. The locking moat can have, for example, a "keyhole" cross-sectional shape or a circular cross-sectional shape. The locking moat can be formed by, for example, stamping or chemical etching. In another embodiment of the invention, the locking feature is a locking region.
    Type: Grant
    Filed: May 3, 1994
    Date of Patent: December 23, 1997
    Assignee: Amkor Electronics, Inc.
    Inventor: Robert C. Marrs
  • Patent number: 5583378
    Abstract: A ball grid array package and low cost method for manufacture of the same is disclosed herein. The ball grid array package includes a thermal conductor which is a linearly co-extensive outer layer of an interconnection substrate and forms the outer surface of the ball grid array package. An integrated circuit chip is positioned on the underside of the package in a well region. The well region is either formed directly in the interconnection substrate or is formed by the application of a dam. The well region is then filled with an insulating encapsulant material to a predetermined level.
    Type: Grant
    Filed: May 16, 1994
    Date of Patent: December 10, 1996
    Assignee: Amkor Electronics, Inc.
    Inventors: Robert C. Marrs, Ronald J. Molnar
  • Patent number: 5485037
    Abstract: An inexpensive packaged integrated circuit with improved heat dissipative capacity and electrical performance. In one embodiment, the packaged integrated circuit includes a semiconductor die, a plurality of electrically conductive package leads, a thermal induction plate and a plurality of electrically conductive bond wires. A surface of the thermal induction plate may remain exposed outside the package. The thermal induction plate reduces package lead inductance and provides shielding of electromagnetic radiation that can cause electromagnetic interference. Preferably, holes are formed through the thermal induction plate to enhance flow of the package material during formation of a package and provide interlocking of the package to the remainder of the integrated circuit. In another embodiment, the packaged integrated circuit further includes a heat sink having a surface exposed to the exterior of the package.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: January 16, 1996
    Assignee: Amkor Electronics, Inc.
    Inventor: Robert C. Marrs
  • Patent number: 5483100
    Abstract: An integrated circuit package, and a method for forming the integrated circuit package, including a single layer or multilayer substrate in which interconnection vias are formed is described. Laser energy is swept across a surface of a mask in which holes have been formed. Laser energy passing through the holes of the mask forms vias in a substrate held in place below the mask. The laser energy is swept at such a speed and is maintained at such an energy level that the laser energy forms vias in the substrate, but does not penetrate a set of leads attached to the substrate. Vias may be formed in this way by either a mask imaging, contact mask or conformal mask technique. The laser energy is emitted from a non-thermal (e.g., excimer) laser. The substrate is formed of an organic (e.g., epoxy) resin. The resin may include reinforcing fibers (e.g., aramid fibers). Substrates may be formed on one or both sides of the set of leads.
    Type: Grant
    Filed: June 2, 1992
    Date of Patent: January 9, 1996
    Assignees: Amkor Electronics, Inc., Teijin Limited
    Inventors: Robert C. Marrs, Tadashi Hirakawa
  • Patent number: 5482898
    Abstract: An inexpensive packaged integrated circuit with improved heat dissipative capacity and electrical performance. In one embodiment, the packaged integrated circuit includes a semiconductor die, a plurality of electrically conductive package leads, a thermal induction plate and a plurality of electrically conductive bond wires. A surface of the thermal induction plate may remain exposed outside the package. The thermal induction plate reduces package lead inductance and provides shielding of electromagnetic radiation that can cause electromagnetic interference. Preferably, holes are formed through the thermal induction plate to enhance flow of the package material during formation of a package and provide interlocking of the package to the remainder of the integrated circuit. In another embodiment, the packaged integrated circuit further includes a heat sink having a surface exposed to the exterior of the package.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: January 9, 1996
    Assignee: Amkor Electronics, Inc.
    Inventor: Robert C. Marrs
  • Patent number: 5478007
    Abstract: According to the invention, a method and structure for flip chip interconnection of an integrated circuit chip to a substrate is provided. The method and structure of the invention overcome the problems associated with interconnecting the chip to the substrate by wirebonding and are less expensive than prior art flip chip interconnection methods and structures. Conventional integrated circuit chips that have been made using wafer fabrication processes for wirebonding chip-level interconnection are electrically connected to a substrate using a flip chip interconnection. Conventional wirebonding equipment can be used to bump chips for use in the invention.
    Type: Grant
    Filed: May 11, 1994
    Date of Patent: December 26, 1995
    Assignee: Amkor Electronics, Inc.
    Inventor: Robert C. Marrs
  • Patent number: 5455462
    Abstract: An integrated circuit package including a heat sink is disclosed. The package incorporates an sealing (or locking) ring located circumferentially around the heat sink to provide a better seal between the encapsulant and heat sink and to reduce the possibility that contaminants from outside the package will reach the interior semiconductor die. A stress relief section is formed in the package leads and a dielectric adhesive material is used to attach the package leads to a heat sink surface. The dielectric adhesive creates a secure bond between leads and heat sink, allows heat transfer from the leads to the heat sink, and prevents shorting of the leads to the heat sink.
    Type: Grant
    Filed: November 15, 1993
    Date of Patent: October 3, 1995
    Assignee: Amkor Electronics, Inc.
    Inventor: Robert C. Marrs
  • Patent number: 5378869
    Abstract: An integrated circuit package, and a method for forming the integrated circuit package, including a single layer or multilayer substrate in which interconnection vias are formed is described. Laser energy is swept across a surface of a mask in which holes have been formed. Laser energy passing through the holes of the mask forms vias in a substrate held in place below the mask. The laser energy is swept at such a speed and is maintained at such an energy level that the laser energy forms vias in the substrate, but does not penetrate a set of leads attached to the substrate. Vias may be formed in this way by either a mask imaging, contact mask or conformal mask technique. The laser energy is emitted from a non-thermal (e.g., excimer) laser. The substrate is formed of an organic (e.g., epoxy) resin. The resin may include reinforcing fibers (e.g., aramid fibers). Substrates may be formed on one or both sides of the set of leads.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: January 3, 1995
    Assignees: Amkor Electronics, Inc., Teijin Limited
    Inventors: Robert C. Marrs, Tadashi Hirakawa
  • Patent number: 5355283
    Abstract: A ball grid array is formed by mounting and electrically connecting one or more electronic devices to a substrate in which vias are formed to interconnect electrically conductive traces formed in a surface of the substrate to solder ball pads formed at an opposite surface of the substrate. The vias are formed by mechanical or laser drilling. Solder balls are formed on each of the pads and are reflow-attached to, for instance, a printed circuit board. The electronic components can include one or more integrated circuit chips, as well as passive components. The electronic components are attached to the substrate using wirebonding, TAB or flip chip connection. An encapsulating material is applied to encapsulate the electronic devices.
    Type: Grant
    Filed: April 14, 1993
    Date of Patent: October 11, 1994
    Assignees: Amkor Electronics, Inc., Teijin Limited
    Inventors: Robert C. Marrs, Tadashi Hirakawa
  • Patent number: 5328870
    Abstract: An improved integrated circuit package including a heat sink and an improved method for making the package is disclosed. The package incorporates an improved sealing (or locking) ring located circumferentially around the heat sink to provide a better seal between the encapsulant and heat sink and to reduce the possibility that contaminants from outside the package will reach the interior semiconductor die. A stress relief section is formed in the package leads and a dielectric adhesive material is used to attach the package leads to a heat sink surface. The dielectric adhesive creates a secure bond between leads and heat sink, allows heat transfer from the leads to the heat sink, and prevents shorting of the leads to the heat sink.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: July 12, 1994
    Assignee: Amkor Electronics, Inc.
    Inventor: Robert C. Marrs