Abstract: Apparatus and methods for performing parity checking in an environment in which devices which perform parity checking and those which do not are connected to the same synchronous bus. The bus includes a parity enable line, which carries a parity enable signal indicating that the device transmitting data on the bus is a parity device which provides the parity of the data it transmits, a parity line, which carries the parity of the data being transmitted, and a parity error line which carries a parity error signal indicating whether the receiving device detected a parity error. The data is transmitted in a first bus cycle, the parity enable signal and the parity are transmitted in the following bus cycle, and the receiving device transmits the parity error signal in the next bus cycle after that.

Abstract: An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components.