Abstract: A clock circuit for a microcomputer having a clock input, a halt mode state output and an interrupt input, comprises: a clock pulse generator having an output, a switch for applying a pulsed output to the interrupt input of the microcomputer to indicate a start of operation; a latch receptive of the output of the switch to change from a first state to a second state, gates receptive of the output of the clock pulse generator and the latch for applying clock pulses to the microcomputer when the logic is in the second state and preventing the application of clock pulses to the microcomputer when the logic is in the first state and circuitry for applying the halt mode state output to the logic circuit to disable same from the second state to the first state.