Abstract: A method of assigning quantization values for use during the compression of images is disclosed. The method includes constructing a non-parametric model during a training phase based on relationships between image characteristics, quantization values, and required bit resources to encode images. The model is built by considering a wide sample of images. The consideration includes determining the temporal and spatial characteristics of the images, compressing the images over a range of quantization values, and recording the resultant required bit resource on a per characterization/quantization level basis. Once built, the model may be used during real time compression by determining the characteristics of the input image and using the allocated resource to find a corresponding match in the non-parametric model. The associated quantization value is then assigned to the input image.

Abstract: The present invention relates to stable HPV capsomeres which express at least one virus-neutralizing conformational epitope of a native HPV L1 protein which are substantially incapable of assembly into virus-like particles. These capsomeres, because of their smaller size, and immunogenic properties are well suited for use in HPV vaccines and as diagnostic agents. Moreover, because of their smaller size (relative to VLPs), these stable capsomeres may be easily purified and should result in HPV vaccines of enhanced homogeneity.

Abstract: The present invention is directed to a method of expressing the papillomavirus capsid protein coding sequence in a cell using an expression system under conditions facilitating expression of the protein in the cell. In another aspect of the invention, it has been discovered that virus-like particle(s) (VLPs), fragment(s), capsomer(s) or portion(s) thereof are formed from the papillomavirus capsid protein. It was further discovered that the virus-like particle(s) comprises antigenic characteristics similar to those of native infectious papillomavirus particles. In one embodiment of the invention, there is provided a method of expressing the L1 major capsid protein of human papillomavirus type-6 (HPV-6) and type-11 (HPV-11) in Sf-9 insect cells using the baculovirus expression system, and the production of type 6 (HPV-6), type-11 (HPV-11), type-16 (HPV-16) and type-18 (HPV-18) virus-like particles.

Abstract: This invention allows each of a plurality of windows to use its own distinct datatype and format while more than one window is being displayed on a monitor screen of a computer video graphics system. Different windows can use full color or pseudocolor frame buffer organizations, can use overlay planes or not, and can have other differences in the interpretation of the pixel values without affecting each other. Window dependent pixel datatypes are provided by means of a lookup table that is contained in logic between the frame buffer and the colormap/DAC that drives the monitor. This lookup table contains descriptors for pixel datatypes. It is indexed by a window number that is specified for each pixel. The pixel datatype descriptor accessed at each pixel is then used to control logic that processes that pixel value to create an index for the colormap. This allows each window to specify its own pixel datatype and format, that is used to interpret the pixels contained in the window.

Abstract: A method and a device for distinguishing which pixels are to be displayed in a set of overlapping, rectangular windows in video graphics display are provided. Windows are specified as a priority ordered list of rectangles or other shapes, so that each window is computed as being visible at those pixels that are inside its rectangle but outside the rectangles of all higher priority windows. The number of rectangles required is equal to the number of rectangular windows, irrespective of the degree of overlap.

Abstract: A circuit for generating an N by M pixel sprite cursor having edge extension features which are clipped to only appear in preselected windows on a video display. The circuit provides edge extension by extending the pattern appearing in the pixels located along the four edges of the sprite cursor towards the corresponding boundaries of the display. The circuit clips the cursor to preselected windows by determining on a pixel-by pixel basis which window owns the pixel to be displayed and whether the window will permit a cursor to appear in it.

Abstract: Pixel formats and a pixel mapping unit for use in a computer graphics terminal which provides an address input to a color look-up table. The disclosed pixel formats can be used to conserve frame buffer memory, color table memory, or both. For example, the formats support pseudo color or full color mapping, overlay planes, and color table bank select while using a minimum amount of memory. A valid plane feature is also supported, which can be used to enable rapid clearing of a window. The pixel mapping unit is especially handy in supporting multiple windows, because a unique mapping configuration word, which specifies how pixels are to be interpreted, may be specified for each window.

Abstract: A method and apparatus for updating the copies of state table values of a video data path chip set for a computer graphics system is provided. The apparatus uses off screen bitmap memory or other dual-ported memory in a frame buffer to store a shadow copy of the state that is stored in the video data path chips. The state tables include such things as color lookup tables, window definitions and cursors. A semaphore is used to prevent screen glitches caused by updating state tables from the copy of state table values that are partially modified. The state tables are loaded into the chips during vertical retrace, when the screen is being blanked. Before the CPU begins to update the shadow copy in the frame buffer, it claims the semaphore. If a vertical retrace occurs before the CPU has completed updating the frame buffer, the chips are not loaded during that vertical retrace. Before the chips start loading, a system timing chip claims the semaphore.

Abstract: A video display system for a computer graphics workstation expands the color look-up table external to the video digital-to-analog (DAC) chip by providing, for each color, a bank of one or more color look-up table extender chips. The extender chips for a given color are connected in series and the banks are connected in parallel between the frame buffer and the video DAC chip. On a pixel-by-pixel basis, and for each color channel, one of the look-up tables afforded by the extender chips or the video DAC chip is accessed using an index from the frame buffer.

Abstract: This invention adds a window dependent base value to the pixel values read from a frame buffer or other source of pixel values. The base value points to the base of the colormap for that window, which is allocated within a larger, physical colormap. Each window can access physical colormap entries starting at its base value and extending up to the base value plus the maximum pixel value used in that window. Adding a window dependent base value to the pixel values for each window allows different windows to use different colormaps, each of which can be allocated to any contiguous set of entries in the physical colormap. Each window's virtual colormap need only use as many entries in the physical colormap as there are entries in the virtual colormap. Finally, virtual colormaps can be compacted or otherwise reallocated in the physical colormap without requiring changes in the pixel values stored in the frame buffer. Only the colormap base values stored for each window need be changed.

Abstract: An image generator (38) in a workstation draws its image data from a pair of frame buffers (32 and 34). The selection between the frame buffers is made by a multiplexer circuit (42) that can switch between frame buffers (32 and 34) on a pixel-by-pixel basis, i.e., different frame buffers can be used during different parts of the same scan frame of a monitor (18) in the image generator (38). A selection-signal source (46), which provides the selection signals for the multiplexer circuit (42), includes a window detector (56), which compares the outputs of counters (72 and 74) that represent the monitor scan position with the outputs of registers (62, 64, 66, and 68) that represent the boundaries of windows used by respective applications that the workstation is running. The source (46) thereby identifies the windows in which the pixel currently being displayed is located, and it employs a priority circuit (76) to identify the one such window having the highest priority.

Abstract: A system and method for testing nodes, or test points, of an integrated circuit are presented. The invention includes a test/load bus which is used to sequentially load test data and other data onto the integrated circuit chip, to sample test points and to read data previously loaded onto the chip. The test/load bus and its control logic are used for both testing the chip and for loading and dumping data from the chip so that the test capability adds little to the area of the chip.

Abstract: Circuitry to enable pixel signals, which represent information that is stored in a first section of memory (and which information defines an image, or images to be viewed on a CRT display) to be transferred to a different section of memory and in the course of the transferral be: expanded or reduced in number; and/or rotated, by arbitrary angles from the original orientation of the image; and/or have the holes, or missing pixels, which occur because of the rotation by the arbitrary angles filled in, or replaced.

Abstract: A programmable logic array includes a decoder section and an encoder section connected by a plurality of minterm conductors. The decoder section receives a plurality of input signals and in response selects appropriate ones of the minterm conductors. The selection of the minterm conductors enable the encoder selection to transmit a plurality of output signal on respective output conductors. The decoder and encoder sections include a plurality of stages, each controlling a minterm conductor and output conductor in response to the input signals and the selection of the minterm conductor. The stages include control transistors that are connected between a node, to which the respective minterm and output conductors are connected, and switches which enable and disable the control transistors. The nodes are initially precharged while the switches disable the respective transistors. After precharge, the switches enable the transistors in the decoder and encoder section respectively.

Abstract: The present circuit arrangement is principally directed to scrolling of a region or regions on a video display and includes a bit map memory, at least one address generation and control signal circuitry chip, one or more data signal path circuitry chips, timing circuitry and logic circuitry interconnecting the foregoing various sections of circuitry. The present arrangement functions to refresh, scroll and update during each horizontal scan, in response to a plurality of timing cycles, with every other cycle being a refresh cycle and the intervening cycles being either scroll or update cycles. During a refresh cycle there is a burst of signals read from memory and transmitted to a shift register feeding the video screen to effect refreshing a section of the screen. At the same time those signals are used to refresh the memory.

Abstract: A servo circuit for electronically controlling the operation of an electric motor is disclosed. The rotational frequency of the motor is converted into a varying frequency waveform by a tachometer. The tachometer output is applied to a conversion circuit which includes a peak detector that converts the output waveform of the tachometer into a square-wave signal. The square-wave signal is, in turn, connected to one input of an exclusive-OR gate. The peak detector square-wave signal is also applied to a shift register which, after a time delay, applies the same signal to another input of the exclusive-OR gate. With these connections, the exclusive-OR gate produces a square-wave output whose duty cycle is proportional to the speed of the DC motor. This output can then be either amplified and applied directly to the electric motor to drive it, or integrated and applied to an amplifier to drive the motor in accordance with standard servo techniques.

Abstract: A positioning system for a magnetic tape system that utilizes a multiple record recording format wherein positioning data that marks the beginning of record segments, the beginning of the tape medium, and the ending of the tape medium are pre-recorded at one-fourth of the bit density of work data so that positioning data may be more accurately read at a higher tape speed during a record seek mode of operation. The system also includes detector circuitry that is enabled only upon detecting positioning data and that identifies the positioning data as an inter-record mark signal, beginning of tape signal, or an ending of tape signal. A tape drive controller is responsive to the detection circuitry for controlling the speed and direction of the magnetic tape.

Abstract: Valve-positioning apparatus especially adapted for use with fluid-operated spool valves for positioning the spool member of such a valve in a predetermined position whenever the valve is not operating such as upon installation or during shutdown. In the preferred embodiment, the positioning apparatus includes a piston member normally held out of contact with the spool by fluid pressure but urged into contact with the spool to position the spool when fluid pressure fails or is absent. The positioning apparatus may be used on either or both ends of the spool valve.