Abstract: Systems and methods for synchronizing multiple of output clocks. The system includes: a plurality of frequency dividers configured to receive a plurality of input clock signals and produce a plurality of output clock signals, wherein each of the plurality of output clock signals are lower in frequency than a corresponding input clock signal; and a circuit. The circuit is configured to: compare a first output clock signal of the plurality of output clock signals to a second output clock signal of the plurality of output clock signals to determine whether the first output clock signal is synchronized with the second output clock signal, generate a slip signal in response to determining that the first output clock signal is not synchronized with the second output clock signal, and apply the slip signal to the second output clock signal to synchronize the second output clock signal with the first output clock signal.

Abstract: A circuit including a frequency divider configured to receive a plurality of first frequency input clock signals and provide a plurality of second frequency output clock signals, wherein the plurality of second frequency output clock signals are lower in frequency than the plurality of first frequency input clock signals, a phase detector configured to determine a difference between the plurality of second frequency output clock signals, a low pass filter configured to measure a clock signal spacing error associated with the plurality of second frequency output clock signals based on the difference between the plurality of second frequency output clock signals and to generate one or more control signals in response to the clock signal spacing error, and a control unit configured to generate one or more corrected first frequency input clock signals based on the one or more control signals.

Abstract: Systems and methods for synchronizing multiple of output clocks. The system includes: a plurality of frequency dividers configured to receive a plurality of input clock signals and produce a plurality of output clock signals, wherein each of the plurality of output clock signals are lower in frequency than a corresponding input clock signal; and a circuit. The circuit is configured to: compare a first output clock signal of the plurality of output clock signals to a second output clock signal of the plurality of output clock signals to determine whether the first output clock signal is synchronized with the second output clock signal, generate a slip signal in response to determining that the first output clock signal is not synchronized with the second output clock signal, and apply the slip signal to the second output clock signal to synchronize the second output clock signal with the first output clock signal.

Abstract: Systems and methods for synchronizing multiple of output clocks. The system includes: a plurality of frequency dividers configured to receive a plurality of input clock signals and produce a plurality of output clock signals, wherein each of the plurality of output clock signals are lower in frequency than a corresponding input clock signal; and a circuit. The circuit is configured to: compare a first output clock signal of the plurality of output clock signals to a second output clock signal of the plurality of output clock signals to determine whether the first output clock signal is synchronized with the second output clock signal, generate a slip signal in response to determining that the first output clock signal is not synchronized with the second output clock signal, and apply the slip signal to the second output clock signal to synchronize the second output clock signal with the first output clock signal.

Abstract: A circuit including a frequency divider configured to receive a plurality of first frequency input clock signals and provide a plurality of second frequency output clock signals, wherein the plurality of second frequency output clock signals are lower in frequency than the plurality of first frequency input clock signals, a phase detector configured to determine a difference between the plurality of second frequency output clock signals, a low pass filter configured to measure a clock signal spacing error associated with the plurality of second frequency output clock signals based on the difference between the plurality of second frequency output clock signals and to generate one or more control signals in response to the clock signal spacing error, and a control unit configured to generate one or more corrected first frequency input clock signals based on the one or more control signals.